Index: sys/dev/ic/ar5212.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5212.c,v
retrieving revision 1.59
diff -u -p -u -r1.59 ar5212.c
--- sys/dev/ic/ar5212.c 3 Feb 2018 17:17:31 -0000 1.59
+++ sys/dev/ic/ar5212.c 3 Oct 2018 13:23:44 -0000
@@ -235,10 +235,20 @@ ar5k_ar5212_attach(u_int16_t device, voi
hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5424;
hal->ah_radio_5ghz_revision = hal->ah_radio_2ghz_revision =
AR5K_SREV_VER_AR5413;
- } else if (srev == AR5K_SREV_VER_AR2425) {
+ //} else if (srev == AR5K_SREV_VER_AR2425) {
+ } else if (hal->ah_mac_version == (AR5K_SREV_VER_AR2425 >> 4) ||
+ hal->ah_mac_version == (AR5K_SREV_VER_AR2417 >> 4) ||
+ hal->ah_phy_revision == (AR5K_SREV_PHY_2425)) {
hal->ah_radio = AR5K_AR2425;
- hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112;
+ //hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112;
+ hal->ah_single_chip = AH_TRUE;
hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_SC2;
+ //hal->ah_radio_5ghz_revision= AR5K_SREV_RAD_2425;
+ } else if ((hal->ah_mac_version == (AR5K_SREV_VER_AR2424 >> 4)) ||
+ (hal->ah_phy_revision == AR5K_SREV_PHY_5413)) {
+ hal->ah_radio = AR5K_AR5413;
+ hal->ah_single_chip = AH_TRUE;
+ hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
} else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
hal->ah_radio = AR5K_AR5111;
hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5111;
@@ -2871,10 +2881,10 @@ ar5k_ar5212_get_capabilities(struct ath_
if (b)
hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
-#if 0
+//#if 0
if (g)
hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
-#endif
+//#endif
}
/* GPIO */
Index: sys/dev/ic/ar5212reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5212reg.h,v
retrieving revision 1.12
diff -u -p -u -r1.12 ar5212reg.h
--- sys/dev/ic/ar5212reg.h 30 Jul 2008 07:15:39 -0000 1.12
+++ sys/dev/ic/ar5212reg.h 3 Oct 2018 13:23:45 -0000
@@ -456,6 +456,7 @@
*/
#define AR5K_AR5212_DCU_MISC(_n) AR5K_AR5212_DCU(_n, 0x1100)
#define AR5K_AR5212_DCU_MISC_BACKOFF 0x000007ff
+#define AR5K_AR5212_DCU_MISC_FRAG_WAIT 0x00000100
#define AR5K_AR5212_DCU_MISC_BACKOFF_FRAG 0x00000200
#define AR5K_AR5212_DCU_MISC_HCFPOLL_ENABLE 0x00000800
#define AR5K_AR5212_DCU_MISC_BACKOFF_PERSIST 0x00001000
@@ -1099,6 +1100,8 @@ typedef enum {
#define AR5K_AR5212_PHY_SLMT_32MHZ 0x0000007f
#define AR5K_AR5212_PHY_SCAL 0x9878
#define AR5K_AR5212_PHY_SCAL_32MHZ 0x0000000e
+#define AR5K_AR5212_PHY_SCAL_32MHZ_2417 0x0000000a
+#define AR5K_AR5212_PHY_SCAL_32MHZ_HB63 0x00000032
/*
* PHY PLL control register
Index: sys/dev/ic/ar5xxx.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5xxx.c,v
retrieving revision 1.63
diff -u -p -u -r1.63 ar5xxx.c
--- sys/dev/ic/ar5xxx.c 31 Jan 2018 11:27:03 -0000 1.63
+++ sys/dev/ic/ar5xxx.c 3 Oct 2018 13:23:45 -0000
@@ -86,6 +86,7 @@ u_int32_t ar5k_ar5110_chan2athchan(HAL_
HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *);
HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *);
+HAL_BOOL ar5k_ar2425_channel(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags);
HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
@@ -889,6 +890,13 @@ ar5k_eeprom_init(struct ath_hal *hal)
ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
}
+
+ AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
+
+ if ((hal->ah_mac_version == (AR5K_SREV_VER_AR2425 >> 4)) && val)
+ ee->ee_is_hb63 = AH_TRUE;
+ else
+ ee->ee_is_hb63 = AH_FALSE;
/*
* Get conformance test limit values
@@ -1109,6 +1117,8 @@ ar5k_channel(struct ath_hal *hal, HAL_CH
ret = ar5k_ar5110_channel(hal, channel);
else if (hal->ah_radio == AR5K_AR5111)
ret = ar5k_ar5111_channel(hal, channel);
+ else if (hal->ah_radio == AR5K_AR2425)
+ ret = ar5k_ar2425_channel(hal, channel);
else
ret = ar5k_ar5112_channel(hal, channel);
@@ -1263,6 +1273,45 @@ ar5k_ar5112_channel(struct ath_hal *hal,
AR5K_PHY_WRITE(0x27, data & 0xff);
AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
+
+ return (AH_TRUE);
+}
+
+HAL_BOOL
+ar5k_ar2425_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
+{
+ u_int32_t data, data0, data2;
+ u_int16_t c;
+
+ data = data0 = data2 = 0;
+ c = channel->c_channel + hal->ah_chanoff;
+
+ /*
+ * Set the channel on the AR2425
+ */
+ if (c < 4800) {
+ data0 = ar5k_bitswap((c - 2272), 8);
+ data2 = 0;
+ } else if ((c - (c % 5)) != 2 || c > 5435) {
+ if (!(c % 20) && c < 5120)
+ data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8);
+ else if (!(c % 10))
+ data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8);
+ else if (!(c % 5))
+ data0 = ar5k_bitswap((c - 4800) / 5, 8);
+ else
+ return (AH_FALSE);
+
+ data2 = ar5k_bitswap(1, 2);
+ } else {
+ data0 = ar5k_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
+ data2 = ar5k_bitswap(0, 2);
+ }
+
+ data = (data0 << 4) | (data2 << 2) | 0x1001;
+
+ AR5K_PHY_WRITE(0x27, data & 0xff);
+ AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
return (AH_TRUE);
}
Index: sys/dev/ic/ar5xxx.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5xxx.h,v
retrieving revision 1.60
diff -u -p -u -r1.60 ar5xxx.h
--- sys/dev/ic/ar5xxx.h 25 Aug 2017 12:17:27 -0000 1.60
+++ sys/dev/ic/ar5xxx.h 3 Oct 2018 13:23:45 -0000
@@ -623,6 +623,8 @@ struct ar5k_gain {
#define AR5K_EEPROM_INFO_CKSUM 0xffff
#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
+#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
+
#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
#define AR5K_EEPROM_VERSION_3_0 0x3000
#define AR5K_EEPROM_VERSION_3_1 0x3001
@@ -765,6 +767,8 @@ struct ar5k_eeprom_info {
int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES];
int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES];
+
+ HAL_BOOL ee_is_hb63;
};
/*
@@ -1235,7 +1239,10 @@ struct ar5k_srev_name {
#define AR5K_SREV_VER_AR5414 0xa5
#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-Express */
#define AR5K_SREV_VER_AR5418 0xca /* PCI-Express */
-#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-Express */
+//#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-Express */
+#define AR5K_SREV_VER_AR2425 0xe0 /* PCI-Express (Swan, was 0xe2) */
+#define AR5K_SREV_VER_AR2417 0xf0 /* PCI-Express (Nala) */
+
#define AR5K_SREV_VER_UNSUPP 0xff
#define AR5K_SREV_RAD_5110 0x00
@@ -1249,8 +1256,12 @@ struct ar5k_srev_name {
#define AR5K_SREV_RAD_SC0 0x56
#define AR5K_SREV_RAD_SC1 0x63
#define AR5K_SREV_RAD_SC2 0xa2
+#define AR5K_SREV_RAD_5413 0x60
+#define AR5K_SREV_RAD_2425 0xa2
#define AR5K_SREV_RAD_5133 0xc0
#define AR5K_SREV_RAD_UNSUPP 0xff
+#define AR5K_SREV_PHY_5413 0x61
+#define AR5K_SREV_PHY_2425 0x70
#define AR5K_DEVID_AR2413 0x001a
#define AR5K_DEVID_AR5413 0x001b
Hi all,
Many thanks for your support and reply!
I am not Profi (I have experience < 1year with OpenBSD and C
Programming.), that why its will take me a lot of time to fix and try
something.
After Mr. Sperling first review of my Code ... I have made few fixes.
In attachment you can see my new patch. Please, try it and send me your
feedback.
Its working for me. (*no more ERROR: ath0 unable to reset hardware*)
My dmesg output:
ath0 at pci3 dev 0 function 0 "Atheros AR5424" rev 0x11: apic 2 int 18
ath0: AR5424 14.2 phy 7.0 rf 10.2 eeprom 5.3, WOR0W, address
00:22:5f:54:aa:50
My pcidump output:
8:0:0: Atheros AR5424
0x0000: Vendor ID: 168c Product ID: 001c
0x0004: Command: 0107 Status: 0010
0x0008: Class: 02 Subclass: 00 Interface: 00 Revision: 11
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line
Size: 10
0x0010: BAR mem 64bit addr: 0x00000000fa000000/0x00010000
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00005001
0x002c: Subsystem Vendor ID: 11ad Product ID: 6303
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: 0a Min Gnt: 00 Max Lat: 00
0x0040: Capability 0x01: Power Management
State: D0
0x0050: Capability 0x05: Message Signalled Interrupts (MSI)
0x0060: Capability 0x10: PCI Express
Link Speed: 2.5 / 2.5 GT/s Link Width: x1 / x1
0x0100: Enhanced Capability 0x01: Advanced Error Reporting
0x0140: Enhanced Capability 0x02: Virtual Channel Capability
0x0090: Capability 0x11: Extended Message Signalled Interrupts
(MSI-X)
Now I can scan all networks around me without error:
# doas ifconfig ath0 scan
ath0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> mtu 1500
lladdr 00:22:5f:54:aa:50
index 2 priority 4 llprio 3
groups: wlan
media: IEEE802.11 autoselect (OFDM54 mode 11g)
status: no network
ieee80211: nwid RUDEUS chan 1 bssid e0:28:6d:41:65:f3 wpakey
wpaprotos wpa2 wpaakms psk wpaciphers ccmp wpagroupcipher ccmp
nwid "Vodafone Hotspot" chan 1 bssid 52:28:6d:41:65:f3
*0%* HT-MCS23 short_preamble,short_slottime
nwid Carames3 chan 1 bssid 5c:49:79:1b:b8:76 *0%*
HT-MCS15 privacy,short_preamble,short_slottime,wpa2
nwid "Vodafone Homespot" chan 1 bssid 62:28:6d:41:65:f3
*0%* HT-MCS23 short_preamble,short_slottime
nwid RUDEUS chan 1 bssid e0:28:6d:41:65:f3 *0%*
HT-MCS23 privacy,short_preamble,short_slottime,wpa2
But you can see that 0% of Wi-Fi power, and I don't know why ? Any ideas ?
Many thanks for strong Support!
Oleg Pahl
On 10/05/18 22:42, Erling Westenvik wrote:
> On Fri, Oct 05, 2018 at 05:12:33PM +0200, Stefan Sperling wrote:
>> On Fri, Oct 05, 2018 at 04:53:40PM +0200, deface@posteo.de wrote:
>>> I try to make new driver for AR5424* WiFi Module (ath0) becouse of a lot
>>> of issues on my Fujitsu Esprimo Mobile U9210 Laptop. (Just not working
>>> out of the box)
> I have two U9210's and would love to see support for the AR5424.
> However, you might be better off by simply replacing the card. On one of
> my two U9210's I replaced it with a working AR9281/athn(4) 802.11n.
> Accessing the card is quite easy and requires only unscrewing two or
> four screws and then carefully bending open the bezel above the
> keyboard.
>
> On Fri, Oct 05, 2018 at 05:12:33PM +0200, Stefan Sperling wrote:
>> Please fix the existing driver instead of adding a new one.
>> A patch was submitted for this device some time ago but there was
>> never any follow-up after the first round of review process:
>> https://marc.info/?t=151707061600004&r=1&w=2
> Actually that thread was the same OP. Right, Oleg?
>
>> You could use that patch as a starting point. But please note that it's
>> unclear whether some or all of these changes were copied from GPL code.
>> It would be better to base such changes on the FreeBSD driver which
>> seems to support this device as well.
>>
>>> Could you be so kind to answer:
>>>
>>> 1. How can I try my new Driver without Build Kernel each time.
>> No. You have to rebuild the kernel each time.
>>
>>> 2. What kind of tools can I use for Debuging WiFi ... (just examples)
>> Many. Start working on it and ask again when you run into specific problems.
>>
>>> 3. Any info about OpenBSD Drivers ? Developers Guides (Just for OpenBSD)
>> See https://www.openbsd.org/papers/eurobsdcon2017-device-drivers.pdf
>> and other presentations mentioned therein.
> There is this article (also by Stefan) from 2014 as well:
>
> http://undeadly.org/cgi?action=article&sid=20140721125235
>
> Good luck. Please let me know if I can be of any help in testing.
>
> Erling
>
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