Re: Network VF 2

/dts-v1/;

/ {

compatible = "starfive,visionfive-v2", "starfive,jh7110";
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "StarFive VisionFive V2";
osc {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x16e3600>;
phandle = <0xf>;
};
clk-ext-camera {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x16e3600>;
phandle = <0x31>;
};
gmac1_rmii_refin {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
phandle = <0x10>;
};
gmac1_rgmii_rxin {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x7735940>;
phandle = <0x11>;
};
i2stx_bclk_ext {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
phandle = <0x12>;
};
i2stx_lrck_ext {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2ee00>;
phandle = <0x13>;
};
i2srx_bclk_ext {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
phandle = <0x14>;
};
i2srx_lrck_ext {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2ee00>;
phandle = <0x15>;
};
tdm_ext {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2ee0000>;
phandle = <0x16>;
};
mclk_ext {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
phandle = <0x17>;
};
jtag_tck_inner {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
phandle = <0x18>;
};
bist_apb {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
phandle = <0x19>;
};
gmac0_rmii_refin {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
phandle = <0x1b>;
};
gmac0_rgmii_rxin {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x7735940>;
phandle = <0x1c>;
};
clk_rtc {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x8000>;
phandle = <0x1a>;
};
hdmitx0_pixelclk {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x11b3dc40>;
phandle = <0x1e>;
};
mipitx_dphy_rxesc {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x989680>;
phandle = <0x1f>;
};
mipitx_dphy_txbytehs {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x11b3dc40>;
phandle = <0x20>;
};
wm8960_mclk {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x1770000>;
};
ac108_mclk {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x16e3600>;
};
opp-table-0 {

compatible = "operating-points-v2";
opp-shared;
phandle = <0x6>;
opp-375000000 {

opp-hz = <0x0 0x165a0bc0>;
opp-microvolt = <0xc3500>;
};
opp-500000000 {

opp-hz = <0x0 0x1dcd6500>;
opp-microvolt = <0xc3500>;
};
opp-750000000 {

opp-hz = <0x0 0x2cb41780>;
opp-microvolt = <0xc3500>;
opp-suspend;
};
opp-1500000000 {

opp-hz = <0x0 0x59682f00>;
opp-microvolt = <0xfde80>;
};
opp-312500000 {

opp-hz = <0x0 0x12a05f20>;
opp-microvolt = <0xc3500>;
};
opp-417000000 {

opp-hz = <0x0 0x18daea40>;
opp-microvolt = <0xc3500>;
};
opp-625000000 {

opp-hz = <0x0 0x2540be40>;
opp-microvolt = <0xc3500>;
opp-suspend;
};
opp-1250000000 {

opp-hz = <0x0 0x4a817c80>;
opp-microvolt = <0xf4240>;
};
};
cpus {

#address-cells = <0x1>;
#size-cells = <0x0>;
timebase-frequency = <0x3d0900>;
cpu-map {

cluster0 {

core0 {

cpu = <0x1>;
};
core1 {

cpu = <0x2>;
};
core2 {

cpu = <0x3>;
};
core3 {

cpu = <0x4>;
};
};
};
cpu@0 {

compatible = "sifive,s7", "riscv";
reg = <0x0>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x2000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x4000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x5>;
riscv,isa = "rv64imac_zba_zbb";
tlb-split;
#cooling-cells = <0x2>;
status = "disabled";
phandle = <0x27>;
interrupt-controller {

#interrupt-cells = <0x1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
phandle = <0xa>;
};
};
cpu@1 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x1>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x5>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
#cooling-cells = <0x2>;
status = "okay";
operating-points-v2 = <0x6>;
cpu-supply = <0x7>;
clocks = <0x8 0x1>;
clock-names = "cpu";
phandle = <0x1>;
interrupt-controller {

#interrupt-cells = <0x1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
phandle = <0xb>;
};
};
cpu@2 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x2>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x5>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
#cooling-cells = <0x2>;
status = "okay";
operating-points-v2 = <0x6>;
phandle = <0x2>;
interrupt-controller {

#interrupt-cells = <0x1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
phandle = <0xc>;
};
};
cpu@3 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x3>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x5>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
#cooling-cells = <0x2>;
status = "okay";
operating-points-v2 = <0x6>;
phandle = <0x3>;
interrupt-controller {

#interrupt-cells = <0x1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
phandle = <0xd>;
};
};
cpu@4 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x4>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x5>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
#cooling-cells = <0x2>;
status = "okay";
operating-points-v2 = <0x6>;
phandle = <0x4>;
interrupt-controller {

#interrupt-cells = <0x1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
phandle = <0xe>;
};
};
};
soc {

compatible = "simple-bus";
interrupt-parent = <0x9>;
#address-cells = <0x2>;
#size-cells = <0x2>;
#clock-cells = <0x1>;
ranges;
cache-controller@2010000 {

compatible = "sifive,fu740-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
reg-names = "control", "sideband";
interrupts = <0x1 0x3 0x4 0x2>;
cache-block-size = <0x40>;
cache-level = <0x2>;
cache-sets = <0x800>;
cache-size = <0x200000>;
cache-unified;
phandle = <0x5>;
};
aon_syscon@17010000 {

compatible = "syscon";
reg = <0x0 0x17010000 0x0 0x1000>;
phandle = <0x39>;
};
multi-phyctrl@10210000 {

compatible = "starfive,phyctrl";
reg = <0x0 0x10210000 0x0 0x10000>;
phandle = <0x45>;
};
pcie1-phyctrl@10220000 {

compatible = "starfive,phyctrl";
reg = <0x0 0x10220000 0x0 0x10000>;
phandle = <0x48>;
};
stg_syscon@10240000 {

compatible = "syscon";
reg = <0x0 0x10240000 0x0 0x1000>;
phandle = <0x23>;
};
sys_syscon@13030000 {

compatible = "syscon";
reg = <0x0 0x13030000 0x0 0x1000>;
phandle = <0x1d>;
};
clint@2000000 {

compatible = "riscv,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
interrupts-extended = <0xa 0x3 0xa 0x7 0xb 0x3 0xb 0x7 0xc 0x3 0xc 0x7 0xd 0x3 0xd 0x7 0xe 0x3 0xe 0x7>;
#interrupt-cells = <0x1>;
};
plic@c000000 {

compatible = "riscv,plic0";
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
interrupts-extended = <0xa 0xb 0xb 0xb 0xb 0x9 0xc 0xb 0xc 0x9 0xd 0xb 0xd 0x9 0xe 0xb 0xe 0x9>;
interrupt-controller;
#interrupt-cells = <0x1>;
riscv,max-priority = <0x7>;
riscv,ndev = <0x88>;
phandle = <0x9>;
};
clock-controller {

compatible = "starfive,jh7110-clkgen";
reg = <0x0 0x13020000 0x0 0x10000 0x0 0x10230000 0x0 0x10000 0x0 0x17000000 0x0 0x10000>;
reg-names = "sys", "stg", "aon";
clocks = <0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c>;
clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "jtag_tck_inner", "bist_apb", "clk_rtc", "gmac0_rmii_refin", "gmac0_rgmii_rxin";
#clock-cells = <0x1>;
starfive,sys-syscon = <0x1d 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34>;
status = "okay";
phandle = <0x8>;
};
clock-controller@295C0000 {

compatible = "starfive,jh7110-clk-vout";
reg = <0x0 0x295c0000 0x0 0x10000>;
reg-names = "vout";
clocks = <0x1e 0x1f 0x20 0x8 0x3a 0x8 0x3d>;
clock-names = "hdmitx0_pixelclk", "mipitx_dphy_rxesc", "mipitx_dphy_txbytehs", "vout_src", "vout_top_ahb";
resets = <0x21 0x2b>;
reset-names = "vout_src";
#clock-cells = <0x1>;
power-domains = <0x22 0x4>;
status = "okay";
phandle = <0x4e>;
};
clock-controller@19810000 {

compatible = "starfive,jh7110-clk-isp";
reg = <0x0 0x19810000 0x0 0x10000>;
reg-names = "isp";
#clock-cells = <0x1>;
clocks = <0x8 0x10a 0x8 0x33 0x8 0x34 0x8 0x35>;
clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp", "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x", "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", "u0_sft7110_noc_bus_clk_isp_axi";
resets = <0x21 0x29 0x21 0x2a 0x21 0x1c>;
reset-names = "rst_isp_top_n", "rst_isp_top_axi", "rst_isp_noc_bus_n";
power-domains = <0x22 0x5>;
status = "okay";
phandle = <0x38>;
};
spi@13010000 {

compatible = "cdns,qspi-nor";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x0 0x13010000 0x0 0x10000 0x0 0x21000000 0x0 0x400000>;
interrupts = <0x19>;
clocks = <0x8 0x5a 0x8 0x58 0x8 0xa 0x8 0x57 0x8 0x59>;
clock-names = "clk_ref", "clk_apb", "ahb1", "clk_ahb", "clk_src";
resets = <0x21 0x3e 0x21 0x3d 0x21 0x3f>;
cdns,fifo-depth = <0x100>;
cdns,fifo-width = <0x4>;
cdns,trigger-address = <0x0>;
spi-max-frequency = <0xee6b280>;
nor-flash@0 {

compatible = "jedec,spi-nor";
reg = <0x0>;
cdns,read-delay = <0x5>;
spi-max-frequency = <0x5f5e100>;
cdns,tshsl-ns = <0x1>;
cdns,tsd2d-ns = <0x1>;
cdns,tchsh-ns = <0x1>;
cdns,tslch-ns = <0x1>;
partitions {

compatible = "fixed-partitions";
#address-cells = <0x1>;
#size-cells = <0x1>;
spl@0 {

reg = <0x0 0x40000>;
};
uboot@100000 {

reg = <0x100000 0x300000>;
};
data@f00000 {

reg = <0xf00000 0x100000>;
};
};
};
};
otp@17050000 {

compatible = "starfive,jh7110-otp";
reg = <0x0 0x17050000 0x0 0x10000>;
clock-frequency = <0x3d0900>;
clocks = <0x8 0xe4>;
clock-names = "apb";
};
usbdrd {

compatible = "starfive,jh7110-cdns3";
reg = <0x0 0x10210000 0x0 0x1000 0x0 0x10200000 0x0 0x1000>;
clocks = <0x8 0x5f 0x8 0xc4 0x8 0xc2 0x8 0xc3 0x8 0xbf 0x8 0xc1 0x8 0xc0>;
clock-names = "125m", "app", "lpm", "stb", "apb", "axi", "utmi";
resets = <0x21 0x8a 0x21 0x88 0x21 0x87 0x21 0x89>;
reset-names = "pwrup", "apb", "axi", "utmi";
starfive,stg-syscon = <0x23 0x4 0xc4 0x148 0x1f4>;
starfive,sys-syscon = <0x1d 0x18>;
status = "okay";
#address-cells = <0x2>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
ranges;
starfive,usb2-only;
dr_mode = "peripheral";
usb@10100000 {

compatible = "cdns,usb3";
reg = <0x0 0x10100000 0x0 0x10000 0x0 0x10110000 0x0 0x10000 0x0 0x10120000 0x0 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <0x64 0x6c 0x6e>;
interrupt-names = "host", "peripheral", "otg";
phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
maximum-speed = "super-speed";
};
};
timer@13050000 {

compatible = "starfive,jh7110-timers";
reg = <0x0 0x13050000 0x0 0x10000>;
interrupts = <0x45 0x46 0x47 0x48>;
interrupt-names = "timer0", "timer1", "timer2", "timer3";
clocks = <0x8 0x7d 0x8 0x7e 0x8 0x7f 0x8 0x80 0x8 0x7c>;
clock-names = "timer0", "timer1", "timer2", "timer3", "apb_clk";
resets = <0x21 0x76 0x21 0x77 0x21 0x78 0x21 0x79 0x21 0x75>;
reset-names = "timer0", "timer1", "timer2", "timer3", "apb_rst";
clock-frequency = <0x16e3600>;
status = "okay";
};
wdog@13070000 {

compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
interrupts = <0x44>;
interrupt-names = "wdog";
clocks = <0x8 0x7b 0x8 0x7a>;
clock-names = "core_clk", "apb_clk";
resets = <0x21 0x6d 0x21 0x6e>;
reset-names = "rst_apb", "rst_core";
timeout-sec = <0xf>;
status = "okay";
};
rtc@17040000 {

compatible = "starfive,jh7110-rtc";
reg = <0x0 0x17040000 0x0 0x10000>;
interrupts = <0xa 0xb 0xc>;
interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
clocks = <0x8 0xe5 0x8 0xe8>;
clock-names = "pclk", "cal_clk";
resets = <0x21 0xa7 0x21 0xa5 0x21 0xa6>;
reset-names = "rst_osc", "rst_apb", "rst_cal";
rtc,cal-clock-freq = <0xf4240>;
status = "okay";
};
power-controller@17030000 {

compatible = "starfive,jh7110-pmu";
reg = <0x0 0x17030000 0x0 0x10000>;
interrupts = <0x6f>;
#power-domain-cells = <0x1>;
status = "okay";
phandle = <0x22>;
};
serial@10000000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x10000000 0x0 0x10000>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
clocks = <0x8 0x92 0x8 0x91>;
clock-names = "baudclk", "apb_pclk";
resets = <0x21 0x53 0x21 0x54>;
interrupts = <0x20>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x24>;
};
serial@10010000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x10010000 0x0 0x10000>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
clocks = <0x8 0x94 0x8 0x93>;
clock-names = "baudclk", "apb_pclk";
resets = <0x21 0x55 0x21 0x56>;
interrupts = <0x21>;
status = "disabled";
};
serial@10020000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x10020000 0x0 0x10000>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
clocks = <0x8 0x96 0x8 0x95>;
clock-names = "baudclk", "apb_pclk";
resets = <0x21 0x57 0x21 0x58>;
interrupts = <0x22>;
status = "disabled";
};
serial@12000000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
clocks = <0x8 0x98 0x8 0x97>;
clock-names = "baudclk", "apb_pclk";
resets = <0x21 0x59 0x21 0x5a>;
interrupts = <0x2d>;
status = "disabled";
};
serial@12010000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x12010000 0x0 0x10000>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
clocks = <0x8 0x9a 0x8 0x99>;
clock-names = "baudclk", "apb_pclk";
resets = <0x21 0x5b 0x21 0x5c>;
interrupts = <0x2e>;
status = "disabled";
};
serial@12020000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x12020000 0x0 0x10000>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
clocks = <0x8 0x9c 0x8 0x9b>;
clock-names = "baudclk", "apb_pclk";
resets = <0x21 0x5d 0x21 0x5e>;
interrupts = <0x2f>;
status = "disabled";
};
dma-controller@16050000 {

compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
reg = <0x0 0x16050000 0x0 0x10000>;
clocks = <0x8 0xd9 0x8 0xda 0x8 0x60>;
clock-names = "core-clk", "cfgr-clk", "stg_clk";
resets = <0x21 0x85 0x21 0x86 0x21 0x1e>;
reset-names = "rst_axi", "rst_ahb", "rst_stg";
interrupts = <0x49>;
#dma-cells = <0x2>;
dma-channels = <0x4>;
snps,dma-masters = <0x1>;
snps,data-width = <0x3>;
snps,num-hs-if = <0x38>;
snps,block-size = <0x10000 0x10000 0x10000 0x10000>;
snps,priority = <0x0 0x1 0x2 0x3>;
snps,axi-max-burst-len = <0x10>;
status = "okay";
phandle = <0x3d>;
};
gpio@13040000 {

compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
reg-names = "control";
clocks = <0x8 0x70>;
resets = <0x21 0x2>;
interrupts = <0x56>;
interrupt-controller;
#gpio-cells = <0x2>;
ngpios = <0x40>;
status = "okay";
phandle = <0x2c>;
i2c0-pins {

phandle = <0x29>;
i2c0-pins-scl {

starfive,pins = <0x39>;
starfive,pinmux = <0x2ac 0xc 0x7000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x5>;
starfive,pin-gpio-din = <0x9>;
};
i2c0-pins-sda {

starfive,pins = <0x3a>;
starfive,pinmux = <0x2ac 0xf 0x38000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x6>;
starfive,pin-gpio-din = <0xa>;
};
};
i2c5-pins {

phandle = <0x2f>;
i2c5-pins-scl {

starfive,pins = <0x13>;
starfive,pinmux = <0x29c 0x1d 0xe0000000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x2a>;
starfive,pin-gpio-din = <0x4f>;
};
i2c5-pins-sda {

starfive,pins = <0x14>;
starfive,pinmux = <0x2a0 0x0 0x7 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x2b>;
starfive,pin-gpio-din = <0x50>;
};
};
i2c6-pins {

phandle = <0x30>;
i2c6-pins-scl {

starfive,pins = <0x10>;
starfive,pinmux = <0x29c 0x14 0x700000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x2e>;
starfive,pin-gpio-din = <0x56>;
};
i2c6-pins-sda {

starfive,pins = <0x11>;
starfive,pinmux = <0x29c 0x17 0x3800000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x2f>;
starfive,pin-gpio-din = <0x57>;
};
};
pwmdac0-pins {

phandle = <0x3e>;
pwmdac0-pins-left {

starfive,pins = <0x21>;
starfive,pinmux = <0x2a4 0x9 0xe00 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x1c>;
starfive,pin-gpio-doen = <0x0>;
};
pwmdac0-pins-right {

starfive,pins = <0x22>;
starfive,pinmux = <0x2a4 0xc 0x7000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x1d>;
starfive,pin-gpio-doen = <0x0>;
};
};
pwm-pins {

phandle = <0x43>;
pwm_ch0-pins {

starfive,pins = <0x2e>;
starfive,pinmux = <0x2a8 0xf 0x38000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x18>;
starfive,pin-gpio-doen = <0x9>;
};
pwm_ch1-pins {

starfive,pins = <0x3b>;
starfive,pinmux = <0x2ac 0x12 0x1c0000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x19>;
starfive,pin-gpio-doen = <0xa>;
};
};
ssp0-pins {

phandle = <0x44>;
ssp0-pins_tx {

starfive,pins = <0x34>;
starfive,pinmux = <0x2ac 0x0 0x3 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x20>;
starfive,pin-gpio-doen = <0x0>;
};
ssp0-pins_rx {

starfive,pins = <0x35>;
starfive,pinmux = <0x2ac 0x2 0xc 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
starfive,pin-gpio-din = <0x1c>;
};
ssp0-pins_clk {

starfive,pins = <0x30>;
starfive,pinmux = <0x2a8 0x15 0xe00000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x1e>;
starfive,pin-gpio-doen = <0x0>;
};
ssp0-pins_cs {

starfive,pins = <0x31>;
starfive,pinmux = <0x2a8 0x18 0x7000000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x1f>;
starfive,pin-gpio-doen = <0x0>;
};
};
pcie0_perst_default {

perst-pins {

starfive,pins = <0x1a>;
starfive,pinmux = <0x2a0 0x12 0x1c0000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x1>;
starfive,pin-gpio-doen = <0x0>;
};
};
pcie0_perst_active {

perst-pins {

starfive,pins = <0x1a>;
starfive,pinmux = <0x2a0 0x12 0x1c0000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x0>;
};
};
pcie0_wake_default {

phandle = <0x46>;
wake-pins {

starfive,pins = <0x20>;
starfive,pinmux = <0x2a4 0x6 0x1c0 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
};
};
pcie0_clkreq_default {

phandle = <0x47>;
clkreq-pins {

starfive,pins = <0x1b>;
starfive,pinmux = <0x2a0 0x15 0xe00000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
};
};
pcie1_perst_default {

perst-pins {

starfive,pins = <0x1c>;
starfive,pinmux = <0x2a0 0x18 0x7000000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x1>;
starfive,pin-gpio-doen = <0x0>;
};
};
pcie1_perst_active {

perst-pins {

starfive,pins = <0x1c>;
starfive,pinmux = <0x2a0 0x18 0x7000000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x0>;
};
};
pcie1_wake_default {

phandle = <0x49>;
wake-pins {

starfive,pins = <0x15>;
starfive,pinmux = <0x2a0 0x3 0x38 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
};
};
pcie1_clkreq_default {

phandle = <0x4a>;
clkreq-pins {

starfive,pins = <0x1d>;
starfive,pinmux = <0x2a0 0x1b 0x38000000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
};
};
usb-pins {

drive-vbus-pin {

starfive,pins = <0x19>;
starfive,pinmux = <0x2a0 0xf 0x38000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x7>;
starfive,pin-gpio-doen = <0x0>;
};
};
i2srx-pins {

phandle = <0x40>;
i2srx-pins0 {

starfive,pins = <0x3d>;
starfive,pinmux = <0x2ac 0x18 0x7000000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
starfive,pin-gpio-din = <0x17>;
};
};
i2s-clk0 {

phandle = <0x3f>;
i2s-clk0_bclk {

starfive,pins = <0x26>;
starfive,pinmux = <0x2a4 0x17 0x3800000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-din = <0x21 0x1f>;
starfive,pin-gpio-doen = <0x1>;
};
i2s-clk0_lrclk {

starfive,pins = <0x3f>;
starfive,pinmux = <0x2ac 0x1e 0xc0000000 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-din = <0x22 0x20>;
starfive,pin-gpio-doen = <0x1>;
};
};
i2stx-pins {

phandle = <0x42>;
i2stx-pins0 {

starfive,pins = <0x2c>;
starfive,pinmux = <0x2a8 0x9 0xe00 0x0>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-dout = <0x45>;
starfive,pin-gpio-doen = <0x0>;
};
};
uart0-pins {

phandle = <0x24>;
uart0-pins-tx {

starfive,pins = <0x5>;
starfive,pin-ioconfig = <0x7>;
starfive,pin-gpio-dout = <0x14>;
starfive,pin-gpio-doen = <0x0>;
};
uart0-pins-rx {

starfive,pins = <0x6>;
starfive,pinmux = <0x2b0 0x0 0x3 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-doen = <0x1>;
starfive,pin-gpio-din = <0xe>;
};
};
i2c2-pins {

phandle = <0x2a>;
i2c2-pins-scl {

starfive,pins = <0x3>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x1e>;
starfive,pin-gpio-din = <0x3b>;
};
i2c2-pins-sda {

starfive,pins = <0x2>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x0>;
starfive,pin-gpio-doen = <0x1f>;
starfive,pin-gpio-din = <0x3c>;
};
};
mmc0-pins {

phandle = <0x36>;
mmc0-pins-rest {

starfive,pins = <0x3e>;
starfive,pinmux = <0x2ac 0x1b 0x38000000 0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0x13>;
starfive,pin-gpio-doen = <0x0>;
};
mmc0-pins-cLK {

starfive,pins = <0x40>;
starfive,pin-ioconfig = <0x2d>;
};
mmc0-pins-cmd {

starfive,pins = <0x41>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data0 {

starfive,pins = <0x42>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data1 {

starfive,pins = <0x43>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data2 {

starfive,pins = <0x44>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data3 {

starfive,pins = <0x45>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data4 {

starfive,pins = <0x46>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data5 {

starfive,pins = <0x47>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data6 {

starfive,pins = <0x48>;
starfive,pin-ioconfig = <0xb>;
};
mmc0-pins-data7 {

starfive,pins = <0x49>;
starfive,pin-ioconfig = <0xb>;
};
};
sdcard1-pins {

phandle = <0x37>;
sdcard1-pins0 {

starfive,pins = <0xa>;
starfive,pinmux = <0x29c 0x2 0x1c 0x0>;
starfive,pin-ioconfig = <0x2d>;
starfive,pin-gpio-dout = <0x37>;
starfive,pin-gpio-doen = <0x0>;
};
sdcard1-pins1 {

starfive,pins = <0x9>;
starfive,pinmux = <0x2b0 0x8 0x700 0x0>;
starfive,pin-ioconfig = <0xb>;
starfive,pin-gpio-dout = <0x39>;
starfive,pin-gpio-doen = <0x13>;
starfive,pin-gpio-din = <0x2c>;
};
sdcard1-pins2 {

starfive,pins = <0xb>;
starfive,pinmux = <0x29c 0x5 0xe0 0x0>;
starfive,pin-ioconfig = <0xb>;
starfive,pin-gpio-dout = <0x3a>;
starfive,pin-gpio-doen = <0x14>;
starfive,pin-gpio-din = <0x2d>;
};
sdcard1-pins3 {

starfive,pins = <0xc>;
starfive,pinmux = <0x29c 0x8 0x700 0x0>;
starfive,pin-ioconfig = <0xb>;
starfive,pin-gpio-dout = <0x3b>;
starfive,pin-gpio-doen = <0x15>;
starfive,pin-gpio-din = <0x2e>;
};
sdcard1-pins4 {

starfive,pins = <0x7>;
starfive,pinmux = <0x2b0 0x2 0x1c 0x0>;
starfive,pin-ioconfig = <0xb>;
starfive,pin-gpio-dout = <0x3c>;
starfive,pin-gpio-doen = <0x16>;
starfive,pin-gpio-din = <0x2f>;
};
sdcard1-pins5 {

starfive,pins = <0x8>;
starfive,pinmux = <0x2b0 0x5 0xe0 0x0>;
starfive,pin-ioconfig = <0xb>;
starfive,pin-gpio-dout = <0x3d>;
starfive,pin-gpio-doen = <0x17>;
starfive,pin-gpio-din = <0x30>;
};
};
inno_hdmi-pins {

phandle = <0x59>;
inno_hdmi-scl {

starfive,pins = <0x0>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0xb>;
starfive,pin-gpio-doen = <0x3>;
starfive,pin-gpio-din = <0x6>;
};
inno_hdmi-sda {

starfive,pins = <0x1>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-dout = <0xc>;
starfive,pin-gpio-doen = <0x4>;
starfive,pin-gpio-din = <0x7>;
};
inno_hdmi-cec-pins {

starfive,pins = <0xe>;
starfive,pin-ioconfig = <0x9>;
starfive,pin-gpio-doen = <0x2>;
starfive,pin-gpio-dout = <0xa>;
starfive,pin-gpio-din = <0x5>;
};
inno_hdmi-hpd-pins {

starfive,pins = <0xf>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-doen = <0x1>;
starfive,pin-gpio-din = <0x8>;
};
};
mclk_ext_pins {

phandle = <0x41>;
mclk_ext_pins {

starfive,pins = <0x4>;
starfive,pin-ioconfig = <0x1>;
starfive,pin-gpio-din = <0x1e>;
starfive,pin-gpio-doen = <0x1>;
};
};
};
gpio@17020000 {

compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
reg-names = "control";
resets = <0x21 0xa2>;
interrupts = <0x55>;
interrupt-controller;
#gpio-cells = <0x2>;
ngpios = <0x4>;
status = "okay";
phandle = <0x62>;
};
tmon@120e0000 {

compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;
interrupts = <0x51>;
clocks = <0x8 0x82 0x8 0x81>;
clock-names = "sense", "bus";
resets = <0x21 0x7c 0x21 0x7b>;
reset-names = "sense", "bus";
#thermal-sensor-cells = <0x0>;
status = "okay";
phandle = <0x25>;
};
thermal-zones {

cpu-thermal {

polling-delay-passive = <0xfa>;
polling-delay = <0x3a98>;
thermal-sensors = <0x25>;
trips {

cpu_alert0 {

temperature = <0x14c08>;
hysteresis = <0x7d0>;
type = "passive";
phandle = <0x26>;
};
cpu_crit {

temperature = <0x186a0>;
hysteresis = <0x7d0>;
type = "critical";
};
};
cooling-maps {

map0 {

trip = <0x26>;
cooling-device = <0x27 0xffffffff 0xffffffff 0x1 0xffffffff 0xffffffff 0x2 0xffffffff 0xffffffff 0x3 0xffffffff 0xffffffff>;
};
};
};
};
trng@1600C000 {

compatible = "starfive,jh7110-trng";
reg = <0x0 0x1600c000 0x0 0x4000>;
clocks = <0x8 0xcd 0x8 0xce>;
clock-names = "hclk", "ahb";
resets = <0x21 0x83>;
interrupts = <0x1e>;
status = "okay";
};
sec_dma@16008000 {

compatible = "arm,pl080", "arm,primecell";
arm,primecell-periphid = <0x41080>;
reg = <0x0 0x16008000 0x0 0x4000>;
reg-names = "sec_dma";
interrupts = <0x1d>;
clocks = <0x8 0xcd 0x8 0xce>;
clock-names = "sec_hclk", "apb_pclk";
resets = <0x21 0x83>;
reset-names = "sec_hre";
lli-bus-interface-ahb1;
mem-bus-interface-ahb1;
memcpy-burst-size = <0x100>;
memcpy-bus-width = <0x20>;
#dma-cells = <0x2>;
status = "okay";
phandle = <0x28>;
};
crypto@16000000 {

compatible = "starfive,jh7110-sec";
reg = <0x0 0x16000000 0x0 0x4000 0x0 0x16008000 0x0 0x4000>;
reg-names = "secreg", "secdma";
interrupts = <0x1c 0x1d>;
interrupt-names = "secirq", "dmairq";
clocks = <0x8 0xcd 0x8 0xce>;
clock-names = "sec_hclk", "sec_ahb";
resets = <0x21 0x83>;
reset-names = "sec_hre";
enable-side-channel-mitigation = "true";
enable-dma = "true";
dmas = <0x28 0x1 0x2 0x28 0x0 0x2>;
dma-names = "sec_m", "sec_p";
status = "okay";
};
i2c@10030000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x10030000 0x0 0x10000>;
clocks = <0x8 0x125 0x8 0x8a>;
clock-names = "ref", "pclk";
resets = <0x21 0x4c>;
interrupts = <0x23>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
auto_calc_scl_lhcnt;
pinctrl-names = "default";
pinctrl-0 = <0x29>;
};
i2c@10040000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x10040000 0x0 0x10000>;
clocks = <0x8 0x126 0x8 0x8b>;
clock-names = "ref", "pclk";
resets = <0x21 0x4d>;
interrupts = <0x24>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
i2c@10050000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x10050000 0x0 0x10000>;
clocks = <0x8 0x127 0x8 0x8c>;
clock-names = "ref", "pclk";
resets = <0x21 0x4e>;
interrupts = <0x25>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
auto_calc_scl_lhcnt;
pinctrl-names = "default";
pinctrl-0 = <0x2a>;
seeed_plane_i2c@45 {

compatible = "seeed_panel";
reg = <0x45>;
port {

endpoint {

remote-endpoint = <0x2b>;
phandle = <0x55>;
};
};
};
tinker_ft5406@38 {

compatible = "tinker_ft5406";
reg = <0x38>;
};
panel_radxa@19 {

compatible = "starfive_jadard";
reg = <0x19>;
reset-gpio = <0x2c 0x17 0x0>;
enable-gpio = <0x2c 0x16 0x0>;
port {

endpoint {

remote-endpoint = <0x2d>;
phandle = <0x56>;
};
};
};
touchscreen@14 {

compatible = "goodix,gt911";
reg = <0x14>;
irq-gpios = <0x2c 0x1e 0x0>;
reset-gpios = <0x2c 0x1f 0x0>;
};
panel_10inch@20 {

compatible = "panel_10inch";
reg = <0x20>;
reset-gpio = <0x2c 0x17 0x0>;
enable-gpio = <0x2c 0x16 0x0>;
port {

endpoint {

remote-endpoint = <0x2e>;
phandle = <0x57>;
};
};
};
};
i2c@12030000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12030000 0x0 0x10000>;
clocks = <0x8 0x128 0x8 0x8d>;
clock-names = "ref", "pclk";
resets = <0x21 0x4f>;
interrupts = <0x30>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
i2c@12040000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12040000 0x0 0x10000>;
clocks = <0x8 0x129 0x8 0x8e>;
clock-names = "ref", "pclk";
resets = <0x21 0x50>;
interrupts = <0x31>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
i2c@12050000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12050000 0x0 0x10000>;
clocks = <0x8 0x12a 0x8 0x8f>;
clock-names = "ref", "pclk";
resets = <0x21 0x51>;
interrupts = <0x32>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
auto_calc_scl_lhcnt;
pinctrl-names = "default";
pinctrl-0 = <0x2f>;
eeprom@50 {

compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <0x10>;
};
axp15060_reg@36 {

compatible = "stf,axp15060-regulator";
reg = <0x36>;
regulators {

ALDO1 {

regulator-boot-on;
regulator-compatible = "mipi_0p9";
regulator-name = "mipi_0p9";
regulator-min-microvolt = <0xdbba0>;
regulator-max-microvolt = <0xdbba0>;
};
ALDO5 {

regulator-boot-on;
regulator-compatible = "hdmi_0p9";
regulator-name = "hdmi_0p9";
regulator-min-microvolt = <0xdbba0>;
regulator-max-microvolt = <0xdbba0>;
};
ALDO3 {

regulator-boot-on;
regulator-compatible = "hdmi_1p8";
regulator-name = "hdmi_1p8";
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
};
ALDO4 {

regulator-boot-on;
regulator-always-on;
regulator-compatible = "sdio_vdd";
regulator-name = "sdio_vdd";
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
phandle = <0x35>;
};
DCDC1 {

regulator-boot-on;
regulator-always-on;
regulator-compatible = "vcc_3v3";
regulator-name = "vcc_3v3";
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
phandle = <0x34>;
};
DCDC2 {

regulator-boot-on;
regulator-always-on;
regulator-compatible = "cpu_vdd";
regulator-name = "cpu_vdd";
regulator-min-microvolt = <0x7a120>;
regulator-max-microvolt = <0x177fa0>;
phandle = <0x7>;
};
};
};
};
i2c@12060000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12060000 0x0 0x10000>;
clocks = <0x8 0x12b 0x8 0x90>;
clock-names = "ref", "pclk";
resets = <0x21 0x52>;
interrupts = <0x33>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
auto_calc_scl_lhcnt;
pinctrl-names = "default";
pinctrl-0 = <0x30>;
imx219@10 {

compatible = "sony,imx219";
reg = <0x10>;
clocks = <0x31>;
clock-names = "xclk";
reset-gpio = <0x2c 0x12 0x0>;
rotation = <0x0>;
orientation = <0x1>;
port {

endpoint {

remote-endpoint = <0x32>;
bus-type = <0x4>;
clock-lanes = <0x4>;
data-lanes = <0x0 0x1>;
lane-polarities = <0x0 0x0 0x0>;
link-frequencies = <0x0 0x1b2e0200>;
phandle = <0x3a>;
};
};
};
imx708@1a {

compatible = "sony,imx708";
reg = <0x1a>;
clocks = <0x31>;
reset-gpio = <0x2c 0x12 0x0>;
port {

endpoint {

remote-endpoint = <0x33>;
data-lanes = <0x1 0x2>;
clock-noncontinuous;
link-frequencies = <0x0 0x1ad27480>;
phandle = <0x3b>;
};
};
};
};
sdio0@16010000 {

compatible = "starfive,jh7110-sdio";
reg = <0x0 0x16010000 0x0 0x10000>;
clocks = <0x8 0x5b 0x8 0x5d>;
clock-names = "biu", "ciu";
resets = <0x21 0x40>;
reset-names = "reset";
interrupts = <0x4a>;
fifo-depth = <0x20>;
fifo-watermark-aligned;
data-addr = <0x0>;
starfive,sys-syscon = <0x1d 0x14 0x1a 0x7c000000>;
status = "okay";
max-frequency = <0x5f5e100>;
card-detect-delay = <0x12c>;
bus-width = <0x8>;
cap-mmc-highspeed;
non-removable;
cap-mmc-hw-reset;
post-power-on-delay-ms = <0xc8>;
vmmc-supply = <0x34>;
vqmmc-supply = <0x35>;
pinctrl-names = "default";
pinctrl-0 = <0x36>;
};
sdio1@16020000 {

compatible = "starfive,jh7110-sdio";
reg = <0x0 0x16020000 0x0 0x10000>;
clocks = <0x8 0x5c 0x8 0x5e>;
clock-names = "biu", "ciu";
resets = <0x21 0x41>;
reset-names = "reset";
interrupts = <0x4b>;
fifo-depth = <0x20>;
fifo-watermark-aligned;
data-addr = <0x0>;
starfive,sys-syscon = <0x1d 0x9c 0x1 0x3e>;
status = "okay";
max-frequency = <0x5f5e100>;
card-detect-delay = <0x12c>;
bus-width = <0x4>;
no-sdio;
no-mmc;
broken-cd;
cap-sd-highspeed;
post-power-on-delay-ms = <0xc8>;
pinctrl-names = "default";
pinctrl-0 = <0x37>;
};
vin_sysctl@19800000 {

compatible = "starfive,jh7110-vin";
reg = <0x0 0x19800000 0x0 0x10000 0x0 0x19810000 0x0 0x10000 0x0 0x19820000 0x0 0x10000 0x0 0x19840000 0x0 0x10000 0x0 0x19870000 0x0 0x30000 0x0 0x11840000 0x0 0x10000 0x0 0x17030000 0x0 0x10000 0x0 0x13020000 0x0 0x10000>;
reg-names = "csi2rx", "vclk", "vrst", "sctrl", "isp", "trst", "pmu", "syscrg";
clocks = <0x38 0x0 0x38 0x6 0x38 0x7 0x38 0xd 0x38 0x2 0x38 0xc 0x38 0x1 0x38 0x8 0x38 0x9 0x38 0xa 0x38 0xb 0x38 0x3 0x38 0x4 0x38 0x5 0x8 0x33 0x8 0x34>;
clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk", "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", "clk_mipi_rx0_pxl", "clk_pixel_clk_if0", "clk_pixel_clk_if1", "clk_pixel_clk_if2", "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in", "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0", "clk_ispcore_2x", "clk_isp_axi";
resets = <0x21 0xc0 0x21 0xc1 0x21 0xc4 0x21 0xc9 0x21 0xca 0x21 0xcb 0x21 0xc5 0x21 0xc6 0x21 0xc7 0x21 0xc8 0x21 0xc2 0x21 0xc3 0x21 0x29 0x21 0x2a>;
reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk", "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0", "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3", "rst_m31dphy_hw", "rst_m31dphy_b09_always_on", "rst_isp_top_n", "rst_isp_top_axi";
starfive,aon-syscon = <0x39 0x0>;
power-domains = <0x22 0x5>;
interrupts = <0x5c 0x57 0x58 0x59 0x5a>;
status = "okay";
ports {

#address-cells = <0x1>;
#size-cells = <0x0>;
port@1 {

reg = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
endpoint@0 {

reg = <0x0>;
remote-endpoint = <0x3a>;
bus-type = <0x4>;
clock-lanes = <0x4>;
data-lanes = <0x0 0x1>;
lane-polarities = <0x0 0x0 0x0>;
status = "okay";
phandle = <0x32>;
};
endpoint@1 {

reg = <0x1>;
remote-endpoint = <0x3b>;
bus-type = <0x4>;
clock-lanes = <0x4>;
data-lanes = <0x0 0x1>;
lane-polarities = <0x0 0x0 0x0>;
status = "okay";
phandle = <0x33>;
};
};
};
};
jpu@11900000 {

compatible = "starfive,jpu";
reg = <0x0 0x13090000 0x0 0x300>;
interrupts = <0xe>;
clocks = <0x8 0x42 0x8 0x43 0x8 0x44 0x8 0x4c>;
clock-names = "axi_clk", "core_clk", "apb_clk", "noc_bus";
resets = <0x21 0x2c 0x21 0x2d 0x21 0x2e>;
reset-names = "rst_axi", "rst_core", "rst_apb";
power-domains = <0x22 0x3>;
status = "okay";
};
vpu_dec@130A0000 {

compatible = "starfive,vdec";
reg = <0x0 0x130a0000 0x0 0x10000>;
interrupts = <0xd>;
clocks = <0x8 0x46 0x8 0x47 0x8 0x48 0x8 0x49 0x8 0x4c>;
clock-names = "axi_clk", "bpu_clk", "vce_clk", "apb_clk", "noc_bus";
resets = <0x21 0x2f 0x21 0x30 0x21 0x31 0x21 0x32 0x21 0x35>;
reset-names = "rst_axi", "rst_bpu", "rst_vce", "rst_apb", "rst_sram";
starfive,vdec_noc_ctrl;
power-domains = <0x22 0x3>;
status = "okay";
};
vpu_enc@130B0000 {

compatible = "starfive,venc";
reg = <0x0 0x130b0000 0x0 0x10000>;
interrupts = <0xf>;
clocks = <0x8 0x4e 0x8 0x4f 0x8 0x50 0x8 0x51 0x8 0x52>;
clock-names = "axi_clk", "bpu_clk", "vce_clk", "apb_clk", "noc_bus";
resets = <0x21 0x36 0x21 0x37 0x21 0x38 0x21 0x39 0x21 0x3a>;
reset-names = "rst_axi", "rst_bpu", "rst_vce", "rst_apb", "rst_sram";
starfive,venc_noc_ctrl;
power-domains = <0x22 0x6>;
status = "okay";
};
reset-controller {

compatible = "starfive,jh7110-reset";
reg = <0x0 0x13020000 0x0 0x10000 0x0 0x10230000 0x0 0x10000 0x0 0x17000000 0x0 0x10000 0x0 0x19810000 0x0 0x10000 0x0 0x295c0000 0x0 0x10000>;
reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
#reset-cells = <0x1>;
status = "okay";
phandle = <0x21>;
};
stmmac-axi-config {

snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <0x100 0x80 0x40 0x20 0x0 0x0 0x0>;
phandle = <0x3c>;
};
ethernet@16030000 {

compatible = "starfive,dwmac", "snps,dwmac-5.10a";
reg = <0x0 0x16030000 0x0 0x10000>;
clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", "pclk", "gtxc", "rmii_rtx";
clocks = <0x8 0x6c 0x8 0xe0 0x8 0x6d 0x8 0xdd 0x8 0xde 0x8 0x6f 0x8 0xdf>;
resets = <0x21 0xa1 0x21 0xa0>;
reset-names = "ahb", "stmmaceth";
interrupts = <0x7 0x6 0x5>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
max-frame-size = <0x2328>;
phy-mode = "rgmii-id";
snps,multicast-filter-bins = <0x40>;
snps,perfect-filter-entries = <0x80>;
rx-fifo-depth = <0x800>;
tx-fifo-depth = <0x800>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <0x3c>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,en-lpi;
snps,write-requests = <0x4>;
snps,read-requests = <0x4>;
snps,burst-map = <0x7>;
snps,txpbl = <0x10>;
snps,rxpbl = <0x10>;
status = "okay";
#address-cells = <0x1>;
#size-cells = <0x0>;
ethernet-phy@0 {

rgmii_sw_dr_2 = <0x0>;
rgmii_sw_dr = <0x3>;
rgmii_sw_dr_rxc = <0x6>;
rxc_dly_en = <0x0>;
rx_delay_sel = <0xa>;
tx_delay_sel_fe = <0x5>;
tx_delay_sel = <0xa>;
tx_inverted_10 = <0x1>;
tx_inverted_100 = <0x1>;
tx_inverted_1000 = <0x1>;
};
};
ethernet@16040000 {

compatible = "starfive,dwmac", "snps,dwmac-5.10a";
reg = <0x0 0x16040000 0x0 0x10000>;
clock-names = "gtx", "tx", "ptp_ref", "stmmaceth", "pclk", "gtxc", "rmii_rtx";
clocks = <0x8 0x64 0x8 0x69 0x8 0x66 0x8 0x61 0x8 0x62 0x8 0x6b 0x8 0x65>;
resets = <0x21 0x43 0x21 0x42>;
reset-names = "ahb", "stmmaceth";
interrupts = <0x4e 0x4d 0x4c>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
max-frame-size = <0x2328>;
phy-mode = "rgmii-id";
snps,multicast-filter-bins = <0x40>;
snps,perfect-filter-entries = <0x80>;
rx-fifo-depth = <0x800>;
tx-fifo-depth = <0x800>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <0x3c>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,en-lpi;
snps,write-requests = <0x4>;
snps,read-requests = <0x4>;
snps,burst-map = <0x7>;
snps,txpbl = <0x10>;
snps,rxpbl = <0x10>;
status = "okay";
#address-cells = <0x1>;
#size-cells = <0x0>;
ethernet-phy@1 {

rgmii_sw_dr_2 = <0x0>;
rgmii_sw_dr = <0x3>;
rgmii_sw_dr_rxc = <0x6>;
tx_delay_sel_fe = <0x5>;
tx_delay_sel = <0x0>;
rxc_dly_en = <0x0>;
rx_delay_sel = <0x2>;
tx_inverted_10 = <0x1>;
tx_inverted_100 = <0x1>;
tx_inverted_1000 = <0x0>;
};
};
gpu@18000000 {

compatible = "img-gpu";
reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130c000 0x0 0x10000>;
clocks = <0x8 0x2d 0x8 0x30 0x8 0x31 0x8 0x2e 0x8 0x2f 0x8 0x32>;
clock-names = "clk_bv", "clk_apb", "clk_rtc", "clk_core", "clk_sys", "clk_axi";
resets = <0x21 0x15 0x21 0x16>;
reset-names = "rst_apb", "rst_doma";
power-domains = <0x22 0x2>;
interrupts = <0x52>;
current-clock = <0x7a1200>;
status = "okay";
};
can@130d0000 {

compatible = "starfive,jh7110-can", "ipms,can";
reg = <0x0 0x130d0000 0x0 0x1000>;
interrupts = <0x70>;
clocks = <0x8 0x73 0x8 0x75 0x8 0x74>;
clock-names = "apb_clk", "core_clk", "timer_clk";
resets = <0x21 0x6f 0x21 0x70 0x21 0x71>;
reset-names = "rst_apb", "rst_core", "rst_timer";
frequency = <0x2625a00>;
starfive,sys-syscon = <0x1d 0x10 0x3 0x8>;
syscon,can_or_canfd = <0x0>;
status = "disabled";
};
can@130e0000 {

compatible = "starfive,jh7110-can", "ipms,can";
reg = <0x0 0x130e0000 0x0 0x1000>;
interrupts = <0x71>;
clocks = <0x8 0x76 0x8 0x78 0x8 0x77>;
clock-names = "apb_clk", "core_clk", "timer_clk";
resets = <0x21 0x72 0x21 0x73 0x21 0x74>;
reset-names = "rst_apb", "rst_core", "rst_timer";
frequency = <0x2625a00>;
starfive,sys-syscon = <0x1d 0x88 0x12 0x40000>;
syscon,can_or_canfd = <0x1>;
status = "disabled";
};
tdm@10090000 {

compatible = "starfive,jh7110-tdm";
reg = <0x0 0x10090000 0x0 0x1000>;
reg-names = "tdm";
clocks = <0x8 0xb8 0x8 0xb9 0x8 0xba 0x16 0x8 0xbb 0x8 0x11>;
clock-names = "clk_tdm_ahb", "clk_tdm_apb", "clk_tdm_internal", "clk_tdm_ext", "clk_tdm", "mclk_inner";
resets = <0x21 0x69 0x21 0x6b 0x21 0x6a>;
reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
dmas = <0x3d 0x14 0x1 0x3d 0x15 0x1>;
dma-names = "rx", "tx";
#sound-dai-cells = <0x0>;
status = "disabled";
};
spdif0@100a0000 {

compatible = "starfive,jh7110-spdif";
reg = <0x0 0x100a0000 0x0 0x1000>;
clocks = <0x8 0x9f 0x8 0xa0 0x8 0x10 0x8 0x11 0x17 0x8 0x12>;
clock-names = "spdif-apb", "spdif-core", "audroot", "mclk_inner", "mclk_ext", "mclk";
resets = <0x21 0x5f>;
reset-names = "rst_apb";
interrupts = <0x54>;
interrupt-names = "tx";
#sound-dai-cells = <0x0>;
status = "disabled";
};
pwmdac@100b0000 {

compatible = "starfive,jh7110-pwmdac";
reg = <0x0 0x100b0000 0x0 0x1000>;
clocks = <0x8 0xc 0x8 0x9d 0x8 0x9e>;
clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
resets = <0x21 0x60>;
reset-names = "rst-apb";
dmas = <0x3d 0x16 0x1>;
dma-names = "tx";
#sound-dai-cells = <0x0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x3e>;
phandle = <0x5f>;
};
i2stx@100c0000 {

compatible = "snps,designware-i2stx";
reg = <0x0 0x100c0000 0x0 0x1000>;
interrupt-names = "tx";
#sound-dai-cells = <0x0>;
dmas = <0x3d 0x1c 0x1>;
dma-names = "rx";
status = "disabled";
};
pdm@100d0000 {

compatible = "starfive,jh7110-pdm";
reg = <0x0 0x100d0000 0x0 0x1000>;
reg-names = "pdm";
clocks = <0x8 0xb6 0x8 0xb7 0x8 0x12 0x17>;
clock-names = "pdm_mclk", "pdm_apb", "clk_mclk", "mclk_ext";
resets = <0x21 0x61 0x21 0x62>;
reset-names = "pdm_dmic", "pdm_apb";
#sound-dai-cells = <0x0>;
};
i2srx_mst@100e0000 {

compatible = "starfive,jh7110-i2srx-master";
reg = <0x0 0x100e0000 0x0 0x1000>;
clocks = <0x8 0xc 0x8 0xaf 0x8 0xb0 0x8 0xb2 0x8 0xb3 0x8 0xb5 0x8 0x12 0x17>;
clock-names = "apb0", "i2srx_apb", "i2srx_bclk_mst", "i2srx_lrck_mst", "i2srx_bclk", "i2srx_lrck", "mclk", "mclk_ext";
resets = <0x21 0x63 0x21 0x64>;
reset-names = "rst_apb_rx", "rst_bclk_rx";
dmas = <0x3d 0x18 0x1>;
dma-names = "rx";
starfive,sys-syscon = <0x1d 0x18 0x34>;
#sound-dai-cells = <0x0>;
status = "disabled";
};
i2srx_3ch@100e0000 {

compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
reg = <0x0 0x100e0000 0x0 0x1000>;
clocks = <0x8 0xc 0x8 0xaf 0x8 0x10 0x8 0x11 0x8 0xb0 0x8 0xb2 0x8 0xb3 0x8 0xb5 0x8 0x12 0x17 0x14 0x15>;
clock-names = "apb0", "3ch-apb", "audioroot", "mclk-inner", "bclk_mst", "3ch-lrck", "rx-bclk", "rx-lrck", "mclk", "mclk_ext", "bclk-ext", "lrck-ext";
resets = <0x21 0x63 0x21 0x64>;
dmas = <0x3d 0x18 0x1>;
dma-names = "rx";
starfive,sys-syscon = <0x1d 0x18 0x34>;
#sound-dai-cells = <0x0>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <0x3f 0x40>;
};
i2stx_4ch0@120b0000 {

compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
reg = <0x0 0x120b0000 0x0 0x1000>;
clocks = <0x8 0x11 0x8 0xa2 0x8 0xa4 0x8 0x12 0x8 0xa5 0x8 0xa7 0x8 0xa1 0x17>;
clock-names = "inner", "bclk-mst", "lrck-mst", "mclk", "bclk0", "lrck0", "i2s_apb", "mclk_ext";
resets = <0x21 0x65 0x21 0x66>;
reset-names = "rst_apb", "rst_bclk";
dmas = <0x3d 0x2f 0x1>;
dma-names = "tx";
#sound-dai-cells = <0x0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x41>;
phandle = <0x5c>;
};
i2stx_4ch1@120c0000 {

compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
reg = <0x0 0x120c0000 0x0 0x1000>;
clocks = <0x8 0x10 0x8 0x11 0x8 0xa9 0x8 0xab 0x8 0x12 0x8 0xac 0x8 0xae 0x8 0x13 0x8 0xc 0x8 0xa8 0x17 0x12 0x13>;
clock-names = "audroot", "mclk_inner", "bclk_mst", "lrck_mst", "mclk", "4chbclk", "4chlrck", "mclk_out", "apb0", "clk_apb", "mclk_ext", "bclk_ext", "lrck_ext";
resets = <0x21 0x67 0x21 0x68>;
dmas = <0x3d 0x30 0x1>;
dma-names = "tx";
#sound-dai-cells = <0x0>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <0x42>;
};
pwm@120d0000 {

compatible = "starfive,jh7110-pwm";
reg = <0x0 0x120d0000 0x0 0x10000>;
reg-names = "control";
clocks = <0x8 0x79>;
resets = <0x21 0x6c>;
starfive,approx-freq = <0x1e8480>;
#pwm-cells = <0x3>;
starfive,npwm = <0x8>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x43>;
};
spdif_transmitter {

compatible = "linux,spdif-dit";
#sound-dai-cells = <0x0>;
status = "disabled";
};
pwmdac-transmitter {

compatible = "starfive,jh7110-pwmdac-dit";
#sound-dai-cells = <0x0>;
status = "okay";
phandle = <0x60>;
};
dmic_codec {

compatible = "dmic-codec";
#sound-dai-cells = <0x0>;
status = "disabled";
};
spi@10060000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10060000 0x0 0x10000>;
clocks = <0x8 0x83>;
clock-names = "apb_pclk";
resets = <0x21 0x45>;
reset-names = "rst_apb";
interrupts = <0x26>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x44>;
spi@0 {

compatible = "rohm,dh2228fv";
pl022,com-mode = <0x1>;
spi-max-frequency = <0x989680>;
reg = <0x0>;
status = "okay";
};
};
spi@10070000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10070000 0x0 0x10000>;
clocks = <0x8 0x84>;
clock-names = "apb_pclk";
resets = <0x21 0x46>;
reset-names = "rst_apb";
interrupts = <0x27>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
spi@10080000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10080000 0x0 0x10000>;
clocks = <0x8 0x85>;
clock-names = "apb_pclk";
resets = <0x21 0x47>;
reset-names = "rst_apb";
interrupts = <0x28>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
spi@12070000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12070000 0x0 0x10000>;
clocks = <0x8 0x86>;
clock-names = "apb_pclk";
resets = <0x21 0x48>;
reset-names = "rst_apb";
interrupts = <0x34>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
spi@12080000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12080000 0x0 0x10000>;
clocks = <0x8 0x87>;
clock-names = "apb_pclk";
resets = <0x21 0x49>;
reset-names = "rst_apb";
interrupts = <0x35>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
spi@12090000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12090000 0x0 0x10000>;
clocks = <0x8 0x88>;
clock-names = "apb_pclk";
resets = <0x21 0x4a>;
reset-names = "rst_apb";
interrupts = <0x36>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
spi@120A0000 {

compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x120a0000 0x0 0x10000>;
clocks = <0x8 0x89>;
clock-names = "apb_pclk";
resets = <0x21 0x4b>;
reset-names = "rst_apb";
interrupts = <0x37>;
arm,primecell-periphid = <0x41022>;
num-cs = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
pcie@2B000000 {

compatible = "starfive,jh7110-pcie", "plda,pci-xpressrich3-axi";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x2b000000 0x0 0x1000000 0x9 0x40000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
starfive,stg-syscon = <0x23 0xc0 0xc4 0x130 0x1b8>;
starfive,phyctrl = <0x45 0x28 0x80>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x8000000 0xc3000000 0x9 0x0 0x9 0x0 0x0 0x40000000>;
msi-parent = <0x9>;
interrupts = <0x38>;
interrupt-controller;
interrupt-names = "msi";
interrupt-parent = <0x9>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x9 0x1 0x0 0x0 0x0 0x2 0x9 0x2 0x0 0x0 0x0 0x3 0x9 0x3 0x0 0x0 0x0 0x4 0x9 0x4>;
resets = <0x21 0x8b 0x21 0x8c 0x21 0x8d 0x21 0x8e 0x21 0x8f 0x21 0x90>;
reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb";
clocks = <0x8 0x60 0x8 0xc8 0x8 0xc6 0x8 0xc7>;
clock-names = "noc", "tl", "axi_mst0", "apb";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x46 0x47>;
reset-gpios = <0x2c 0x1a 0x1>;
};
pcie@2C000000 {

compatible = "starfive,jh7110-pcie", "plda,pci-xpressrich3-axi";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x2c000000 0x0 0x1000000 0x9 0xc0000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
starfive,stg-syscon = <0x23 0x270 0x274 0x2e0 0x368>;
starfive,phyctrl = <0x48 0x28 0x80>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x8000000 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
msi-parent = <0x9>;
interrupts = <0x39>;
interrupt-controller;
interrupt-names = "msi";
interrupt-parent = <0x9>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x9 0x1 0x0 0x0 0x0 0x2 0x9 0x2 0x0 0x0 0x0 0x3 0x9 0x3 0x0 0x0 0x0 0x4 0x9 0x4>;
resets = <0x21 0x91 0x21 0x92 0x21 0x93 0x21 0x94 0x21 0x95 0x21 0x96>;
reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb";
clocks = <0x8 0x60 0x8 0xcb 0x8 0xc9 0x8 0xca>;
clock-names = "noc", "tl", "axi_mst0", "apb";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x49 0x4a>;
reset-gpios = <0x2c 0x1c 0x1>;
};
mailbox@0 {

compatible = "starfive,mail_box";
reg = <0x0 0x13060000 0x0 0x1000>;
clocks = <0x8 0x71>;
clock-names = "clk_apb";
resets = <0x21 0x44>;
reset-names = "mbx_rre";
interrupts = <0x1a 0x1b>;
#mbox-cells = <0x2>;
status = "okay";
phandle = <0x4b>;
};
mailbox_client@0 {

compatible = "starfive,mailbox-test";
mbox-names = "rx", "tx";
mboxes = <0x4b 0x0 0x1 0x4b 0x1 0x0>;
status = "okay";
};
display-subsystem {

compatible = "starfive,jh7110-display", "verisilicon,display-subsystem";
ports = <0x4c>;
status = "okay";
};
dssctrl@295B0000 {

compatible = "starfive,jh7110-dssctrl", "verisilicon,dss-ctrl", "syscon";
reg = <0x0 0x295b0000 0x0 0x90>;
phandle = <0x4d>;
};
tda988x_pin {

compatible = "starfive,tda998x_rgb_pin";
status = "disabled";
};
rgb-output {

compatible = "starfive,jh7110-rgb_output", "verisilicon,rgb-encoder";
status = "disabled";
ports {

#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {

#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x0>;
endpoint@0 {

reg = <0x0>;
remote-endpoint = <0x4c>;
phandle = <0x4f>;
};
};
};
};
dc8200@29400000 {

compatible = "starfive,jh7110-dc8200", "verisilicon,dc8200";
verisilicon,dss-syscon = <0x4d>;
reg = <0x0 0x29400000 0x0 0x100 0x0 0x29400800 0x0 0x2000 0x0 0x17030000 0x0 0x1000>;
interrupts = <0x5f>;
status = "okay";
clocks = <0x8 0x3c 0x8 0x3a 0x8 0x3e 0x8 0x3d 0x4e 0x7 0x4e 0x8 0x4e 0x4 0x4e 0x5 0x4e 0x6 0x8 0x3e 0x4e 0x9 0x1e 0x4e 0x1 0x4e 0x27 0x4e 0x28>;
clock-names = "noc_disp", "vout_src", "top_vout_axi", "top_vout_ahb", "pix_clk", "vout_pix1", "axi_clk", "core_clk", "vout_ahb", "vout_top_axi", "vout_top_lcd", "hdmitx0_pixelclk", "dc8200_pix0", "dc8200_pix0_out", "dc8200_pix1_out";
resets = <0x21 0x2b 0x21 0xe0 0x21 0xe1 0x21 0xe2 0x21 0x1a>;
reset-names = "rst_vout_src", "rst_axi", "rst_ahb", "rst_core", "rst_noc_disp";
port {

#address-cells = <0x1>;
#size-cells = <0x0>;
endpoint@0 {

reg = <0x0>;
remote-endpoint = <0x4f>;
phandle = <0x4c>;
};
endpoint@1 {

reg = <0x1>;
remote-endpoint = <0x50>;
phandle = <0x5a>;
};
endpoint@2 {

reg = <0x2>;
remote-endpoint = <0x51>;
phandle = <0x52>;
};
};
};
dsi-output {

compatible = "starfive,jh7110-display-encoder", "verisilicon,dsi-encoder";
status = "okay";
ports {

#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {

reg = <0x0>;
endpoint {

remote-endpoint = <0x52>;
phandle = <0x51>;
};
};
port@1 {

reg = <0x1>;
endpoint {

remote-endpoint = <0x53>;
phandle = <0x58>;
};
};
};
};
mipi-dphy@295e0000 {

compatible = "starfive,jh7110-mipi-dphy-tx", "m31,mipi-dphy-tx";
reg = <0x0 0x295e0000 0x0 0x10000>;
clocks = <0x4e 0xe>;
clock-names = "dphy_txesc";
resets = <0x21 0xea 0x21 0xeb>;
reset-names = "dphy_sys", "dphy_txbytehs";
#phy-cells = <0x0>;
status = "okay";
phandle = <0x54>;
};
mipi@295d0000 {

compatible = "starfive,jh7110-mipi_dsi", "cdns,dsi";
reg = <0x0 0x295d0000 0x0 0x10000>;
interrupts = <0x62>;
reg-names = "dsi";
clocks = <0x4e 0xb 0x4e 0xa 0x4e 0xd 0x4e 0xc>;
clock-names = "sys", "apb", "txesc", "dpi";
resets = <0x21 0xe3 0x21 0xe4 0x21 0xe5 0x21 0xe6 0x21 0xe7 0x21 0xe8>;
reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc", "dsi_sys", "dsi_txbytehs", "dsi_txesc";
phys = <0x54>;
phy-names = "dphy";
status = "okay";
ports {

#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {

reg = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
endpoint@0 {

reg = <0x0>;
remote-endpoint = <0x55>;
phandle = <0x2b>;
};
endpoint@1 {

reg = <0x1>;
remote-endpoint = <0x56>;
phandle = <0x2d>;
};
endpoint@2 {

reg = <0x2>;
remote-endpoint = <0x57>;
phandle = <0x2e>;
};
};
port@1 {

reg = <0x1>;
endpoint {

remote-endpoint = <0x58>;
phandle = <0x53>;
};
};
};
};
hdmi@29590000 {

compatible = "starfive,jh7110-hdmi", "inno,hdmi";
reg = <0x0 0x29590000 0x0 0x4000>;
interrupts = <0x63>;
status = "okay";
clocks = <0x4e 0x11 0x4e 0xf 0x4e 0x10 0x1e>;
clock-names = "sysclk", "mclk", "bclk", "pclk";
resets = <0x21 0xe9>;
reset-names = "hdmi_tx";
#sound-dai-cells = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <0x59>;
hpd-gpio = <0x2c 0xf 0x0>;
phandle = <0x5d>;
port {

#address-cells = <0x1>;
#size-cells = <0x0>;
endpoint@0 {

reg = <0x0>;
remote-endpoint = <0x5a>;
phandle = <0x50>;
};
};
};
snd-card0 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-AC108-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
snd-card1 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-HDMI-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
simple-audio-card,dai-link@0 {

reg = <0x0>;
format = "i2s";
bitclock-master = <0x5b>;
frame-master = <0x5b>;
mclk-fs = <0x100>;
status = "okay";
cpu {

sound-dai = <0x5c>;
phandle = <0x5b>;
};
codec {

sound-dai = <0x5d>;
};
};
};
snd-card2 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-PDM-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
snd-card3 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
simple-audio-card,dai-link@0 {

reg = <0x0>;
format = "left_j";
bitclock-master = <0x5e>;
frame-master = <0x5e>;
status = "okay";
cpu {

sound-dai = <0x5f>;
phandle = <0x5e>;
};
codec {

sound-dai = <0x60>;
};
};
};
snd-card4 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
snd-card5 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-TDM-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
snd-card6 {

compatible = "simple-audio-card";
simple-audio-card,name = "Starfive-WM8960-Sound-Card";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
e24@0 {

compatible = "starfive,e24";
reg = <0x0 0xc0110000 0x0 0x1000 0x0 0xc0111000 0x0 0x1f000>;
reg-names = "ecmd", "espace";
clocks = <0x8 0xd6 0x8 0xd7 0x8 0xd8>;
clock-names = "clk_rtc", "clk_core", "clk_dbg";
resets = <0x21 0x84>;
reset-names = "e24_core";
starfive,stg-syscon = <0x23>;
interrupt-parent = <0x9>;
firmware-name = "e24_elf";
irq-mode = <0x1>;
mbox-names = "tx", "rx";
mboxes = <0x4b 0x0 0x2 0x4b 0x2 0x0>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
status = "okay";
dsp@0 {

};
};
xrp@0 {

compatible = "cdns,xrp";
reg = <0x0 0x10230000 0x0 0x10000 0x0 0x10240000 0x0 0x10000>;
memory-region = <0x61>;
clocks = <0x8 0xbe>;
clock-names = "core_clk";
resets = <0x21 0x81 0x21 0x82>;
reset-names = "rst_core", "rst_axi";
starfive,stg-syscon = <0x23>;
firmware-name = "hifi4_elf";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x40000000 0x0 0x20000000 0x40000 0xf0000000 0x0 0xf0000000 0x3000000>;
status = "okay";
dsp@0 {

};
};
starfive,jh7110-cpufreq {

compatible = "starfive,jh7110-cpufreq";
clocks = <0x8 0x1>;
clock-names = "cpu_clk";
};
};
aliases {

spi0 = "/soc/spi@13010000";
gpio0 = "/soc/gpio@13040000";
ethernet0 = "/soc/ethernet@16030000";
ethernet1 = "/soc/ethernet@16040000";
mmc0 = "/soc/sdio0@16010000";
mmc1 = "/soc/sdio1@16020000";
serial0 = "/soc/serial@10000000";
serial3 = "/soc/serial@12000000";
i2c0 = "/soc/i2c@10030000";
i2c1 = "/soc/i2c@10040000";
i2c2 = "/soc/i2c@10050000";
i2c3 = "/soc/i2c@12030000";
i2c4 = "/soc/i2c@12040000";
i2c5 = "/soc/i2c@12050000";
i2c6 = "/soc/i2c@12060000";
};
chosen {

linux,initrd-start = <0x0 0x46100000>;
linux,initrd-end = <0x0 0x4c000000>;
stdout-path = "serial0:115200";
#bootargs = "debug console=ttyS0 rootwait";
};
memory@40000000 {

device_type = "memory";
reg = <0x0 0x40000000 0x1 0x0>;
};
reserved-memory {

#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
linux,cma {

compatible = "shared-dma-pool";
reusable;
size = <0x0 0x20000000>;
alignment = <0x0 0x1000>;
alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
linux,cma-default;
};
e24@c0000000 {

no-map;
reg = <0x0 0xc0110000 0x0 0xf0000>;
};
xrpbuffer@f0000000 {

reg = <0x0 0xf0000000 0x0 0x1ffffff 0x0 0xf2000000 0x0 0x1000 0x0 0xf2001000 0x0 0xfff000 0x0 0xf3000000 0x0 0x1000>;
phandle = <0x61>;
};
};
leds {

compatible = "gpio-leds";
led-ack {

gpios = <0x62 0x3 0x0>;
color = <0x2>;
function = "heartbeat";
linux,default-trigger = "heartbeat";
label = "ack";
};
};
gpio-restart {

compatible = "gpio-restart";
gpios = <0x2c 0x23 0x0>;
priority = <0xa0>;
};
};
/dts-v1/;

/ {

compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "StarFive VisionFive 2 v1.3B";
cpus {

#address-cells = <0x1>;
#size-cells = <0x0>;
timebase-frequency = <0x3d0900>;
cpu@0 {

compatible = "sifive,s7", "riscv";
reg = <0x0>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x4000>;
next-level-cache = <0x1>;
riscv,isa = "rv64imac_zba_zbb";
status = "disabled";
phandle = <0x5>;
interrupt-controller {

compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <0x1>;
phandle = <0xb>;
};
};
cpu@1 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x1>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x1>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <0x2>;
clocks = <0x3 0x1>;
clock-names = "cpu";
cpu-supply = <0x4>;
phandle = <0x6>;
interrupt-controller {

compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <0x1>;
phandle = <0xc>;
};
};
cpu@2 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x2>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x1>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <0x2>;
clocks = <0x3 0x1>;
clock-names = "cpu";
cpu-supply = <0x4>;
phandle = <0x7>;
interrupt-controller {

compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <0x1>;
phandle = <0xd>;
};
};
cpu@3 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x3>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x1>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <0x2>;
clocks = <0x3 0x1>;
clock-names = "cpu";
cpu-supply = <0x4>;
phandle = <0x8>;
interrupt-controller {

compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <0x1>;
phandle = <0xe>;
};
};
cpu@4 {

compatible = "sifive,u74-mc", "riscv";
reg = <0x4>;
d-cache-block-size = <0x40>;
d-cache-sets = <0x40>;
d-cache-size = <0x8000>;
d-tlb-sets = <0x1>;
d-tlb-size = <0x28>;
device_type = "cpu";
i-cache-block-size = <0x40>;
i-cache-sets = <0x40>;
i-cache-size = <0x8000>;
i-tlb-sets = <0x1>;
i-tlb-size = <0x28>;
mmu-type = "riscv,sv39";
next-level-cache = <0x1>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <0x2>;
clocks = <0x3 0x1>;
clock-names = "cpu";
cpu-supply = <0x4>;
phandle = <0x9>;
interrupt-controller {

compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <0x1>;
phandle = <0xf>;
};
};
cpu-map {

cluster0 {

core0 {

cpu = <0x5>;
};
core1 {

cpu = <0x6>;
};
core2 {

cpu = <0x7>;
};
core3 {

cpu = <0x8>;
};
core4 {

cpu = <0x9>;
};
};
};
};
opp-table-0 {

compatible = "operating-points-v2";
opp-shared;
phandle = <0x2>;
opp-375000000 {

opp-hz = <0x0 0x165a0bc0>;
opp-microvolt = <0xc3500>;
};
opp-500000000 {

opp-hz = <0x0 0x1dcd6500>;
opp-microvolt = <0xc3500>;
};
opp-750000000 {

opp-hz = <0x0 0x2cb41780>;
opp-microvolt = <0xc3500>;
};
opp-1500000000 {

opp-hz = <0x0 0x59682f00>;
opp-microvolt = <0xfde80>;
};
};
dvp-clock {

compatible = "fixed-clock";
clock-output-names = "dvp_clk";
#clock-cells = <0x0>;
clock-frequency = <0x46cf710>;
phandle = <0x36>;
};
gmac0-rgmii-rxin-clock {

compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
#clock-cells = <0x0>;
clock-frequency = <0x7735940>;
phandle = <0x30>;
};
gmac0-rmii-refin-clock {

compatible = "fixed-clock";
clock-output-names = "gmac0_rmii_refin";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
phandle = <0x2f>;
};
gmac1-rgmii-rxin-clock {

compatible = "fixed-clock";
clock-output-names = "gmac1_rgmii_rxin";
#clock-cells = <0x0>;
clock-frequency = <0x7735940>;
phandle = <0x21>;
};
gmac1-rmii-refin-clock {

compatible = "fixed-clock";
clock-output-names = "gmac1_rmii_refin";
#clock-cells = <0x0>;
clock-frequency = <0x2faf080>;
phandle = <0x20>;
};
hdmitx0-pixel-clock {

compatible = "fixed-clock";
clock-output-names = "hdmitx0_pixelclk";
#clock-cells = <0x0>;
clock-frequency = <0x11b3dc40>;
phandle = <0x39>;
};
i2srx-bclk-ext-clock {

compatible = "fixed-clock";
clock-output-names = "i2srx_bclk_ext";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
phandle = <0x24>;
};
i2srx-lrck-ext-clock {

compatible = "fixed-clock";
clock-output-names = "i2srx_lrck_ext";
#clock-cells = <0x0>;
clock-frequency = <0x2ee00>;
phandle = <0x25>;
};
i2stx-bclk-ext-clock {

compatible = "fixed-clock";
clock-output-names = "i2stx_bclk_ext";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
phandle = <0x22>;
};
i2stx-lrck-ext-clock {

compatible = "fixed-clock";
clock-output-names = "i2stx_lrck_ext";
#clock-cells = <0x0>;
clock-frequency = <0x2ee00>;
phandle = <0x23>;
};
mclk-ext-clock {

compatible = "fixed-clock";
clock-output-names = "mclk_ext";
#clock-cells = <0x0>;
clock-frequency = <0xbb8000>;
phandle = <0x26>;
};
oscillator {

compatible = "fixed-clock";
clock-output-names = "osc";
#clock-cells = <0x0>;
clock-frequency = <0x16e3600>;
phandle = <0x19>;
};
rtc-oscillator {

compatible = "fixed-clock";
clock-output-names = "rtc_osc";
#clock-cells = <0x0>;
clock-frequency = <0x8000>;
phandle = <0x31>;
};
stmmac-axi-config {

snps,lpi_en;
snps,wr_osr_lmt = <0x4>;
snps,rd_osr_lmt = <0x4>;
snps,blen = <0x100 0x80 0x40 0x20 0x0 0x0 0x0>;
phandle = <0x2b>;
};
tdm-ext-clock {

compatible = "fixed-clock";
clock-output-names = "tdm_ext";
#clock-cells = <0x0>;
clock-frequency = <0x2ee0000>;
phandle = <0x13>;
};
soc {

compatible = "simple-bus";
interrupt-parent = <0xa>;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
timer@2000000 {

compatible = "starfive,jh7110-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <0xb 0x3 0xb 0x7 0xc 0x3 0xc 0x7 0xd 0x3 0xd 0x7 0xe 0x3 0xe 0x7 0xf 0x3 0xf 0x7>;
};
cache-controller@2010000 {

compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
reg = <0x0 0x2010000 0x0 0x4000>;
interrupts = <0x1 0x3 0x4 0x2>;
cache-block-size = <0x40>;
cache-level = <0x2>;
cache-sets = <0x800>;
cache-size = <0x200000>;
cache-unified;
phandle = <0x1>;
};
interrupt-controller@c000000 {

compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
interrupts-extended = <0xb 0xb 0xc 0xb 0xc 0x9 0xd 0xb 0xd 0x9 0xe 0xb 0xe 0x9 0xf 0xb 0xf 0x9>;
interrupt-controller;
#interrupt-cells = <0x1>;
#address-cells = <0x0>;
riscv,ndev = <0x88>;
phandle = <0xa>;
};
serial@10000000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <0x3 0x92 0x3 0x91>;
clock-names = "baudclk", "apb_pclk";
resets = <0x3 0x53>;
interrupts = <0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x10>;
};
serial@10010000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <0x3 0x94 0x3 0x93>;
clock-names = "baudclk", "apb_pclk";
resets = <0x3 0x55>;
interrupts = <0x21>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
status = "disabled";
};
serial@10020000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x10020000 0x0 0x10000>;
clocks = <0x3 0x96 0x3 0x95>;
clock-names = "baudclk", "apb_pclk";
resets = <0x3 0x57>;
interrupts = <0x22>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
status = "disabled";
};
i2c@10030000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x10030000 0x0 0x10000>;
clocks = <0x3 0x8a>;
clock-names = "ref";
resets = <0x3 0x4c>;
interrupts = <0x23>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
pinctrl-names = "default";
pinctrl-0 = <0x11>;
};
i2c@10040000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x10040000 0x0 0x10000>;
clocks = <0x3 0x8b>;
clock-names = "ref";
resets = <0x3 0x4d>;
interrupts = <0x24>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
i2c@10050000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x10050000 0x0 0x10000>;
clocks = <0x3 0x8c>;
clock-names = "ref";
resets = <0x3 0x4e>;
interrupts = <0x25>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
pinctrl-names = "default";
pinctrl-0 = <0x12>;
};
tdm@10090000 {

compatible = "starfive,jh7110-tdm";
reg = <0x0 0x10090000 0x0 0x1000>;
clocks = <0x3 0xb8 0x3 0xb9 0x3 0xba 0x3 0xbb 0x3 0x11 0x13>;
clock-names = "tdm_ahb", "tdm_apb", "tdm_internal", "tdm", "mclk_inner", "tdm_ext";
resets = <0x3 0x69 0x3 0x6b 0x3 0x6a>;
dmas = <0x14 0x14 0x14 0x15>;
dma-names = "rx", "tx";
#sound-dai-cells = <0x0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x15>;
};
usb@10100000 {

compatible = "starfive,jh7110-usb";
ranges = <0x0 0x0 0x10100000 0x100000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
starfive,stg-syscon = <0x16 0x4>;
clocks = <0x17 0x4 0x17 0x5 0x17 0x1 0x17 0x3 0x17 0x2>;
clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
resets = <0x17 0xa 0x17 0x8 0x17 0x7 0x17 0x9>;
reset-names = "pwrup", "apb", "axi", "utmi_apb";
status = "okay";
dr_mode = "peripheral";
usb@0 {

compatible = "cdns,usb3";
reg = <0x0 0x10000 0x10000 0x10000 0x20000 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <0x64 0x6c 0x6e>;
interrupt-names = "host", "peripheral", "otg";
phys = <0x18>;
phy-names = "cdns3,usb2-phy";
};
};
phy@10200000 {

compatible = "starfive,jh7110-usb-phy";
reg = <0x0 0x10200000 0x0 0x10000>;
clocks = <0x3 0x5f 0x17 0x6>;
clock-names = "125m", "app_125m";
#phy-cells = <0x0>;
phandle = <0x18>;
};
phy@10210000 {

compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10210000 0x0 0x10000>;
#phy-cells = <0x0>;
phandle = <0x3c>;
};
phy@10220000 {

compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10220000 0x0 0x10000>;
#phy-cells = <0x0>;
phandle = <0x3f>;
};
clock-controller@10230000 {

compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
clocks = <0x19 0x3 0x36 0x3 0x8 0x3 0x5f 0x3 0x2 0x3 0x37 0x3 0x6 0x3 0xb>;
clock-names = "osc", "hifi4_core", "stg_axiahb", "usb_125m", "cpu_bus", "hifi4_axi", "nocstg_bus", "apb_bus";
#clock-cells = <0x1>;
#reset-cells = <0x1>;
phandle = <0x17>;
};
syscon@10240000 {

compatible = "starfive,jh7110-stg-syscon", "syscon";
reg = <0x0 0x10240000 0x0 0x1000>;
phandle = <0x16>;
};
serial@12000000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
clocks = <0x3 0x98 0x3 0x97>;
clock-names = "baudclk", "apb_pclk";
resets = <0x3 0x59>;
interrupts = <0x2d>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
status = "disabled";
};
serial@12010000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x12010000 0x0 0x10000>;
clocks = <0x3 0x9a 0x3 0x99>;
clock-names = "baudclk", "apb_pclk";
resets = <0x3 0x5b>;
interrupts = <0x2e>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
status = "disabled";
};
serial@12020000 {

compatible = "snps,dw-apb-uart";
reg = <0x0 0x12020000 0x0 0x10000>;
clocks = <0x3 0x9c 0x3 0x9b>;
clock-names = "baudclk", "apb_pclk";
resets = <0x3 0x5d>;
interrupts = <0x2f>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
status = "disabled";
};
i2c@12030000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12030000 0x0 0x10000>;
clocks = <0x3 0x8d>;
clock-names = "ref";
resets = <0x3 0x4f>;
interrupts = <0x30>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
i2c@12040000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12040000 0x0 0x10000>;
clocks = <0x3 0x8e>;
clock-names = "ref";
resets = <0x3 0x50>;
interrupts = <0x31>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "disabled";
};
i2c@12050000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12050000 0x0 0x10000>;
clocks = <0x3 0x8f>;
clock-names = "ref";
resets = <0x3 0x51>;
interrupts = <0x32>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
pinctrl-names = "default";
pinctrl-0 = <0x1a>;
pmic@36 {

compatible = "x-powers,axp15060";
reg = <0x36>;
regulators {

dcdc2 {

regulator-always-on;
regulator-min-microvolt = <0x7a120>;
regulator-max-microvolt = <0x177fa0>;
regulator-name = "vdd-cpu";
phandle = <0x4>;
};
};
};
};
i2c@12060000 {

compatible = "snps,designware-i2c";
reg = <0x0 0x12060000 0x0 0x10000>;
clocks = <0x3 0x90>;
clock-names = "ref";
resets = <0x3 0x52>;
interrupts = <0x33>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = "okay";
clock-frequency = <0x186a0>;
i2c-sda-hold-time-ns = <0x12c>;
i2c-sda-falling-time-ns = <0x1fe>;
i2c-scl-falling-time-ns = <0x1fe>;
pinctrl-names = "default";
pinctrl-0 = <0x1b>;
imx219@10 {

compatible = "sony,imx219";
reg = <0x10>;
clocks = <0x1c>;
reset-gpio = <0x1d 0x12 0x0>;
rotation = <0x0>;
orientation = <0x1>;
port {

endpoint {

remote-endpoint = <0x1e>;
bus-type = <0x4>;
clock-lanes = <0x0>;
data-lanes = <0x1 0x2>;
link-frequencies = <0x0 0x1b2e0200>;
phandle = <0x34>;
};
};
};
};
pwm@120d0000 {

compatible = "starfive,jh7110-pwm";
reg = <0x0 0x120d0000 0x0 0x10000>;
clocks = <0x3 0x79>;
resets = <0x3 0x6c>;
#pwm-cells = <0x3>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x1f>;
};
temperature-sensor@120e0000 {

compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;
clocks = <0x3 0x82 0x3 0x81>;
clock-names = "sense", "bus";
resets = <0x3 0x7c 0x3 0x7b>;
reset-names = "sense", "bus";
#thermal-sensor-cells = <0x0>;
phandle = <0x40>;
};
spi@13010000 {

compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
reg = <0x0 0x13010000 0x0 0x10000 0x0 0x21000000 0x0 0x400000>;
interrupts = <0x19>;
clocks = <0x3 0x5a 0x3 0x57 0x3 0x58>;
clock-names = "qspi-ref", "qspi-ahb", "qspi-apb";
resets = <0x3 0x3e 0x3 0x3d 0x3 0x3f>;
reset-names = "qspi", "qspi-ocp", "rstc_ref";
cdns,fifo-depth = <0x100>;
cdns,fifo-width = <0x4>;
cdns,trigger-address = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
flash@0 {

compatible = "jedec,spi-nor";
reg = <0x0>;
cdns,read-delay = <0x5>;
spi-max-frequency = <0xb71b00>;
cdns,tshsl-ns = <0x1>;
cdns,tsd2d-ns = <0x1>;
cdns,tchsh-ns = <0x1>;
cdns,tslch-ns = <0x1>;
partitions {

compatible = "fixed-partitions";
#address-cells = <0x1>;
#size-cells = <0x1>;
spl@0 {

reg = <0x0 0x20000>;
};
uboot@100000 {

reg = <0x100000 0x300000>;
};
data@f00000 {

reg = <0xf00000 0x100000>;
};
};
};
};
clock-controller@13020000 {

compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
clocks = <0x19 0x20 0x21 0x22 0x23 0x24 0x25 0x13 0x26 0x27 0x0 0x27 0x1 0x27 0x2>;
clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "pll0_out", "pll1_out", "pll2_out";
#clock-cells = <0x1>;
#reset-cells = <0x1>;
phandle = <0x3>;
};
syscon@13030000 {

compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
reg = <0x0 0x13030000 0x0 0x1000>;
phandle = <0x29>;
clock-controller {

compatible = "starfive,jh7110-pll";
clocks = <0x19>;
#clock-cells = <0x1>;
phandle = <0x27>;
};
};
pinctrl@13040000 {

compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
clocks = <0x3 0x70>;
resets = <0x3 0x2>;
interrupts = <0x56>;
interrupt-controller;
#interrupt-cells = <0x2>;
gpio-controller;
#gpio-cells = <0x2>;
phandle = <0x1d>;
i2c0-0 {

phandle = <0x11>;
i2c-pins {

pinmux = <0x9001439 0xa00183a>;
bias-disable;
input-enable;
input-schmitt-enable;
};
};
i2c2-0 {

phandle = <0x12>;
i2c-pins {

pinmux = <0x3b007803 0x3c007c02>;
bias-disable;
input-enable;
input-schmitt-enable;
};
};
i2c5-0 {

phandle = <0x1a>;
i2c-pins {

pinmux = <0x4f00a813 0x5000ac14>;
bias-disable;
input-enable;
input-schmitt-enable;
};
};
i2c6-0 {

phandle = <0x1b>;
i2c-pins {

pinmux = <0x5600b810 0x5700bc11>;
bias-disable;
input-enable;
input-schmitt-enable;
};
};
pcie0_wake_default {

wake-pins {

pinmux = <0xff010020>;
bias-disable;
drive-strength = <0x2>;
input-enable;
input-schmitt-disable;
slew-rate = <0x0>;
};
};
pcie0_clkreq_default {

clkreq-pins {

bias-disable;
pinmux = <0xff01001b>;
drive-strength = <0x2>;
input-enable;
input-schmitt-disable;
slew-rate = <0x0>;
};
};
pcie1_wake_default {

wake-pins {

bias-disable;
pinmux = <0xff010015>;
drive-strength = <0x2>;
input-enable;
input-schmitt-disable;
slew-rate = <0x0>;
};
};
pcie1_clkreq_default {

clkreq-pins {

bias-disable;
pinmux = <0xff01001d>;
drive-strength = <0x2>;
input-enable;
input-schmitt-disable;
slew-rate = <0x0>;
};
};
pwm-0 {

phandle = <0x1f>;
pwm-pins {

pinmux = <0xff18242e 0xff19283b>;
bias-disable;
drive-strength = <0xc>;
input-disable;
input-schmitt-disable;
slew-rate = <0x0>;
};
};
tdm0-pins {

phandle = <0x15>;
tdm0-pins-tx {

pinmux = <0xff29002c>;
bias-pull-up;
drive-strength = <0x2>;
input-disable;
input-schmitt-disable;
slew-rate = <0x0>;
};
tdm0-pins-rx {

pinmux = <0x2401043d>;
input-enable;
};
tdm0-pins-sync {

pinmux = <0x2501043f>;
input-enable;
};
tdm0-pins-pcmclk {

pinmux = <0x23010426>;
input-enable;
};
};
uart0-0 {

phandle = <0x10>;
tx-pins {

pinmux = <0xff140005>;
bias-disable;
drive-strength = <0xc>;
input-disable;
input-schmitt-disable;
slew-rate = <0x0>;
};
rx-pins {

pinmux = <0xe000406>;
bias-disable;
drive-strength = <0x2>;
input-enable;
input-schmitt-enable;
slew-rate = <0x0>;
};
};
};
timer@13050000 {

compatible = "starfive,jh7110-timer";
reg = <0x0 0x13050000 0x0 0x10000>;
interrupts = <0x45 0x46 0x47 0x48>;
clocks = <0x3 0x7c 0x3 0x7d 0x3 0x7e 0x3 0x7f 0x3 0x80>;
clock-names = "apb", "ch0", "ch1", "ch2", "ch3";
resets = <0x3 0x75 0x3 0x76 0x3 0x77 0x3 0x78 0x3 0x79>;
reset-names = "apb", "ch0", "ch1", "ch2", "ch3";
};
watchdog@13070000 {

compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
clocks = <0x3 0x7a 0x3 0x7b>;
clock-names = "apb", "core";
resets = <0x3 0x6d 0x3 0x6e>;
};
crypto@16000000 {

compatible = "starfive,jh7110-crypto";
reg = <0x0 0x16000000 0x0 0x4000>;
clocks = <0x17 0xf 0x17 0x10>;
clock-names = "hclk", "ahb";
interrupts = <0x1c>;
resets = <0x17 0x3>;
dmas = <0x28 0x1 0x2 0x28 0x0 0x2>;
dma-names = "tx", "rx";
status = "disabled";
};
dma@16008000 {

compatible = "arm,pl080", "arm,primecell";
arm,primecell-periphid = <0x41080>;
reg = <0x0 0x16008000 0x0 0x4000>;
interrupts = <0x1d>;
clocks = <0x17 0xf 0x17 0x10>;
clock-names = "hclk", "apb_pclk";
resets = <0x17 0x3>;
lli-bus-interface-ahb1;
mem-bus-interface-ahb1;
memcpy-burst-size = <0x100>;
memcpy-bus-width = <0x20>;
#dma-cells = <0x2>;
phandle = <0x28>;
};
rng@1600c000 {

compatible = "starfive,jh7110-trng";
reg = <0x0 0x1600c000 0x0 0x4000>;
clocks = <0x17 0xf 0x17 0x10>;
clock-names = "hclk", "ahb";
resets = <0x17 0x3>;
interrupts = <0x1e>;
};
mmc@16010000 {

compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;
clocks = <0x3 0x5b 0x3 0x5d>;
clock-names = "biu", "ciu";
resets = <0x3 0x40>;
reset-names = "reset";
interrupts = <0x4a>;
fifo-depth = <0x20>;
fifo-watermark-aligned;
data-addr = <0x0>;
starfive,sysreg = <0x29 0x14 0x1a 0x7c000000>;
status = "okay";
max-frequency = <0x5f5e100>;
bus-width = <0x8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
cap-mmc-hw-reset;
post-power-on-delay-ms = <0xc8>;
};
mmc@16020000 {

compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16020000 0x0 0x10000>;
clocks = <0x3 0x5c 0x3 0x5e>;
clock-names = "biu", "ciu";
resets = <0x3 0x41>;
reset-names = "reset";
interrupts = <0x4b>;
fifo-depth = <0x20>;
fifo-watermark-aligned;
data-addr = <0x0>;
starfive,sysreg = <0x29 0x9c 0x1 0x3e>;
status = "okay";
max-frequency = <0x5f5e100>;
bus-width = <0x4>;
no-sdio;
no-mmc;
broken-cd;
cap-sd-highspeed;
post-power-on-delay-ms = <0xc8>;
};
ethernet@16030000 {

compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
reg = <0x0 0x16030000 0x0 0x10000>;
clocks = <0x2a 0x3 0x2a 0x2 0x3 0x6d 0x2a 0x6 0x3 0x6f>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
resets = <0x2a 0x0 0x2a 0x1>;
reset-names = "stmmaceth", "ahb";
interrupts = <0x7 0x6 0x5>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
rx-fifo-depth = <0x800>;
tx-fifo-depth = <0x800>;
snps,multicast-filter-bins = <0x40>;
snps,perfect-filter-entries = <0x8>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <0x2b>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,txpbl = <0x10>;
snps,rxpbl = <0x10>;
starfive,syscon = <0x2c 0xc 0x12>;
status = "okay";
phy-handle = <0x2d>;
phy-mode = "rgmii-id";
starfive,tx-use-rgmii-clk;
assigned-clocks = <0x2a 0x5>;
assigned-clock-parents = <0x2a 0x4>;
mdio {

#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dwmac-mdio";
ethernet-phy@0 {

reg = <0x0>;
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,rx-clk-driver-strength = <0x6>;
motorcomm,rx-data-driver-strength = <0x3>;
rx-internal-delay-ps = <0x5dc>;
tx-internal-delay-ps = <0x5dc>;
phandle = <0x2d>;
};
};
};
ethernet@16040000 {

compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
reg = <0x0 0x16040000 0x0 0x10000>;
clocks = <0x3 0x62 0x3 0x61 0x3 0x66 0x3 0x6a 0x3 0x6b>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
resets = <0x3 0x42 0x3 0x43>;
reset-names = "stmmaceth", "ahb";
interrupts = <0x4e 0x4d 0x4c>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
rx-fifo-depth = <0x800>;
tx-fifo-depth = <0x800>;
snps,multicast-filter-bins = <0x40>;
snps,perfect-filter-entries = <0x8>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <0x2b>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,txpbl = <0x10>;
snps,rxpbl = <0x10>;
starfive,syscon = <0x29 0x90 0x2>;
status = "okay";
phy-handle = <0x2e>;
phy-mode = "rgmii-id";
starfive,tx-use-rgmii-clk;
assigned-clocks = <0x3 0x69>;
assigned-clock-parents = <0x3 0x65>;
mdio {

#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dwmac-mdio";
ethernet-phy@1 {

reg = <0x0>;
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,rx-clk-driver-strength = <0x6>;
motorcomm,rx-data-driver-strength = <0x3>;
rx-internal-delay-ps = <0x12c>;
tx-internal-delay-ps = <0x0>;
phandle = <0x2e>;
};
};
};
dma-controller@16050000 {

compatible = "starfive,jh7110-axi-dma";
reg = <0x0 0x16050000 0x0 0x10000>;
clocks = <0x17 0x1b 0x17 0x1c>;
clock-names = "core-clk", "cfgr-clk";
resets = <0x17 0x5 0x17 0x6>;
interrupts = <0x49>;
#dma-cells = <0x1>;
dma-channels = <0x4>;
snps,dma-masters = <0x1>;
snps,data-width = <0x3>;
snps,block-size = <0x10000 0x10000 0x10000 0x10000>;
snps,priority = <0x0 0x1 0x2 0x3>;
snps,axi-max-burst-len = <0x10>;
phandle = <0x14>;
};
clock-controller@17000000 {

compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
clocks = <0x19 0x2f 0x30 0x3 0x8 0x3 0xb 0x3 0x6c 0x31>;
clock-names = "osc", "gmac0_rmii_refin", "gmac0_rgmii_rxin", "stg_axiahb", "apb_bus", "gmac0_gtxclk", "rtc_osc";
#clock-cells = <0x1>;
#reset-cells = <0x1>;
phandle = <0x2a>;
};
syscon@17010000 {

compatible = "starfive,jh7110-aon-syscon", "syscon";
reg = <0x0 0x17010000 0x0 0x1000>;
#power-domain-cells = <0x1>;
phandle = <0x2c>;
};
pinctrl@17020000 {

compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
resets = <0x2a 0x2>;
interrupts = <0x55>;
interrupt-controller;
#interrupt-cells = <0x2>;
gpio-controller;
#gpio-cells = <0x2>;
};
power-controller@17030000 {

compatible = "starfive,jh7110-pmu";
reg = <0x0 0x17030000 0x0 0x10000>;
interrupts = <0x6f>;
#power-domain-cells = <0x1>;
phandle = <0x37>;
};
csi-bridge@19800000 {

compatible = "starfive,jh7110-csi2rx";
reg = <0x0 0x19800000 0x0 0x10000>;
clocks = <0x32 0x7 0x32 0x6 0x32 0x8 0x32 0x9 0x32 0xa 0x32 0xb>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
resets = <0x32 0x9 0x32 0x4 0x32 0x5 0x32 0x6 0x32 0x7 0x32 0x8>;
reset-names = "sys", "reg_bank", "pixel_if0", "pixel_if1", "pixel_if2", "pixel_if3";
phys = <0x33>;
phy-names = "dphy";
status = "okay";
assigned-clocks = <0x32 0x7>;
assigned-clock-rates = <0x11b3dc40>;
ports {

#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {

reg = <0x0>;
endpoint {

remote-endpoint = <0x34>;
bus-type = <0x4>;
clock-lanes = <0x0>;
data-lanes = <0x1 0x2>;
status = "okay";
phandle = <0x1e>;
};
};
port@1 {

reg = <0x1>;
endpoint {

remote-endpoint = <0x35>;
status = "okay";
phandle = <0x38>;
};
};
};
};
clock-controller@19810000 {

compatible = "starfive,jh7110-ispcrg";
reg = <0x0 0x19810000 0x0 0x10000>;
clocks = <0x3 0x33 0x3 0x34 0x3 0x35 0x36>;
clock-names = "isp_top_core", "isp_top_axi", "noc_bus_isp_axi", "dvp_clk";
resets = <0x3 0x29 0x3 0x2a 0x3 0x1c>;
#clock-cells = <0x1>;
#reset-cells = <0x1>;
power-domains = <0x37 0x5>;
phandle = <0x32>;
};
phy@19820000 {

compatible = "starfive,jh7110-dphy-rx";
reg = <0x0 0x19820000 0x0 0x10000>;
clocks = <0x32 0x3 0x32 0x4 0x32 0x5>;
clock-names = "cfg", "ref", "tx";
resets = <0x32 0x2 0x32 0x3>;
power-domains = <0x2c 0x1>;
#phy-cells = <0x0>;
phandle = <0x33>;
};
camss@19840000 {

compatible = "starfive,jh7110-camss";
reg = <0x0 0x19840000 0x0 0x10000 0x0 0x19870000 0x0 0x30000>;
reg-names = "syscon", "isp";
clocks = <0x32 0x0 0x32 0xd 0x32 0x2 0x32 0xc 0x32 0x1 0x3 0x33 0x3 0x34>;
clock-names = "clk_apb_func", "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", "clk_mipi_rx0_pxl", "clk_ispcore_2x", "clk_isp_axi";
resets = <0x32 0x0 0x32 0x1 0x32 0xa 0x32 0xb 0x3 0x29 0x3 0x2a>;
reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_axird", "rst_axiwr", "rst_isp_top_n", "rst_isp_top_axi";
power-domains = <0x37 0x5>;
interrupts = <0x5c 0x57 0x5a>;
status = "okay";
ports {

#address-cells = <0x1>;
#size-cells = <0x0>;
port@1 {

reg = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
endpoint@1 {

reg = <0x1>;
remote-endpoint = <0x38>;
status = "okay";
phandle = <0x35>;
};
};
};
};
clock-controller@295c0000 {

compatible = "starfive,jh7110-voutcrg";
reg = <0x0 0x295c0000 0x0 0x10000>;
clocks = <0x3 0x3a 0x3 0x3d 0x3 0x3e 0x3 0x3f 0x3 0xa5 0x39>;
clock-names = "vout_src", "vout_top_ahb", "vout_top_axi", "vout_top_hdmitx0_mclk", "i2stx0_bclk", "hdmitx0_pixelclk";
resets = <0x3 0x2b>;
#clock-cells = <0x1>;
#reset-cells = <0x1>;
power-domains = <0x37 0x4>;
};
pcie@2B000000 {

compatible = "starfive,jh7110-pcie";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x2b000000 0x0 0x1000000 0x9 0x40000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
starfive,stg-syscon = <0x16 0xc0 0xc4 0x130 0x1b8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x8000000 0xc3000000 0x9 0x0 0x9 0x0 0x0 0x40000000>;
interrupts = <0x38>;
interrupt-parent = <0xa>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x3a 0x1 0x0 0x0 0x0 0x2 0x3a 0x2 0x0 0x0 0x0 0x3 0x3a 0x3 0x0 0x0 0x0 0x4 0x3a 0x4>;
msi-parent = <0x3b>;
msi-controller;
clocks = <0x3 0x60 0x17 0xa 0x17 0x8 0x17 0x9>;
clock-names = "noc", "tl", "axi_mst0", "apb";
resets = <0x17 0xb 0x17 0xc 0x17 0xd 0x17 0xe 0x17 0xf 0x17 0x10>;
reset-names = "mst0", "slv0", "slv", "brg", "core", "apb";
status = "okay";
pinctrl-names = "default";
reset-gpios = <0x1d 0x1a 0x1>;
phys = <0x3c>;
phandle = <0x3b>;
interrupt-controller {

#address-cells = <0x0>;
#interrupt-cells = <0x1>;
interrupt-controller;
phandle = <0x3a>;
};
};
pcie@2C000000 {

compatible = "starfive,jh7110-pcie";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x2c000000 0x0 0x1000000 0x9 0xc0000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
starfive,stg-syscon = <0x16 0x270 0x274 0x2e0 0x368>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x8000000 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
interrupts = <0x39>;
interrupt-parent = <0xa>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x3d 0x1 0x0 0x0 0x0 0x2 0x3d 0x2 0x0 0x0 0x0 0x3 0x3d 0x3 0x0 0x0 0x0 0x4 0x3d 0x4>;
msi-parent = <0x3e>;
msi-controller;
clocks = <0x3 0x60 0x17 0xd 0x17 0xb 0x17 0xc>;
clock-names = "noc", "tl", "axi_mst0", "apb";
resets = <0x17 0x11 0x17 0x12 0x17 0x13 0x17 0x14 0x17 0x15 0x17 0x16>;
reset-names = "mst0", "slv0", "slv", "brg", "core", "apb";
status = "okay";
pinctrl-names = "default";
reset-gpios = <0x1d 0x1c 0x1>;
phys = <0x3f>;
phandle = <0x3e>;
interrupt-controller {

#address-cells = <0x0>;
#interrupt-cells = <0x1>;
interrupt-controller;
phandle = <0x3d>;
};
};
};
aliases {

ethernet0 = "/soc/ethernet@16030000";
ethernet1 = "/soc/ethernet@16040000";
i2c0 = "/soc/i2c@10030000";
i2c2 = "/soc/i2c@10050000";
i2c5 = "/soc/i2c@12050000";
i2c6 = "/soc/i2c@12060000";
serial0 = "/soc/serial@10000000";
};
chosen {

stdout-path = "serial0:115200n8";
};
memory@40000000 {

device_type = "memory";
reg = <0x0 0x40000000 0x1 0x0>;
};
reserved-memory {

#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
linux,cma {

compatible = "shared-dma-pool";
reusable;
size = <0x0 0x20000000>;
alignment = <0x0 0x1000>;
alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
linux,cma-default;
};
};
thermal-zones {

cpu-thermal {

polling-delay-passive = <0xfa>;
polling-delay = <0x3a98>;
thermal-sensors = <0x40>;
cooling-maps {

};
trips {

cpu_alert0 {

temperature = <0x124f8>;
hysteresis = <0x7d0>;
type = "passive";
};
cpu_crit {

temperature = <0x15f90>;
hysteresis = <0x7d0>;
type = "critical";
};
};
};
};
gpio-restart {

compatible = "gpio-restart";
gpios = <0x1d 0x23 0x0>;
priority = <0xe0>;
};
clk_ext_camera {

compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x16e3600>;
phandle = <0x1c>;
};
};
Zitat von Matthew Ernisse <mernisse@ub3rgeek.net>:

> On Mon, Jul 31, 2023 at 06:48:42PM +0200, Robert Palm said:
>> Cannot get network working on my VisionFive 2 (ping a different machine).
>>
>> Any ideas? Thanks!
>
> Does either side see ARP traffic for the other? (arp -an) Do you
> see traffic leaving your OpenBSD machine? (tcpdump(8) is your
> friend) Check for host firewalls on both sides.
>
>> FreeBSD machine:
>
> [ snip ]
>
>> media: Ethernet autoselect (100baseTX <half-duplex>)
>
> 100/half is a bit odd these days, is this machine able to
> communicate to other things on this ethernet link?
>
> --
> Matthew Ernisse
> https://www.going-flying.com/

Thanks a lot for your suggestions. I will try to check that.


One thing I did notice is that there exist 2 versions of the VF2.

1.2A
PHY0 YT8531C 2 U6 10/100/1000Mbit/sec
PHY1 YT8512C U39 10/100Mbit/sec

1.3B
PHY0 YT8531C U6 10/100/1000Mbit/sec
PHY1 YT8531C U7 10/100/1000Mbit/sec

https://doc-en.rvspace.org/VisionFive2/PDF/RV002_V1.3B_20230208.PDF
https://doc-en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf

I own the 1.2A.

I cannot boot / install OpenBSD using the latest release .dtb file
provided by starfive:

https://github.com/starfive-tech/VisionFive2/releases/download/VF2_v3.1.5/jh7110-visionfive-v2.dtb

So Michael was so kind to send me a
jh7110-starfive-visionfive-2-v1.3b.dtb , c.f.
https://marc.info/?l=openbsd-misc&m=169046816826966&w=2

It works very well to install and boot OpenBSD, but I assume as it is
meant for the 1.3B version the network is causing "problems" with my
version ?

I asked back to Michael and he said network works for him with his
1.3B version.

In general I can see a commit:

* Add support for the Motorcomm YT8521/YT8531 PHYs. Since these PHYs may
need various board-dependent tweaks, pass the device tree node down
to the PHY driver such that we can look at various properties to make
the necessary tweaks. Enable ytphy(4) on riscv64.

So, is the YT8512C supported already ? If not I assume I cannot use my PHY1.

But, the PHY0 should work as it is the same as the 1.3B version uses.

But maybe the .dtb does not fit properly ?

Does anyone has the 1.2A version and can provide a .dtb file that works?

I attached both versions I have as .txt. When I do a diff I see lots
of differences.

Tried to attached two pics showing diffs between 1.3B and 1.2A version
of phy0 and phy1 part (but doesn't seem to be delivered to the mailing
list so I removed them).

Can anyone make sense out of it ?

Many thanks for looking at it.