Hello! Please find this week's update to my update to the (dated) cad/yosys port attached to this email. It includes some updates from the github repository. It is no longer dependent on the cad/abc port. It is part of a set, intended to bring the joy of FPGA development to OpenBSD. cad/prjpeppercorn cad/nextpnr cad/openfpgaloader cad/yosys Thomas
diff --git a/cad/yosys/Makefile b/cad/yosys/Makefile
index c4015435577..816f6488e33 100644
--- a/cad/yosys/Makefile
+++ b/cad/yosys/Makefile
@@ -1,72 +1,29 @@
-COMMENT = framework for Verilog RTL synthesis
-DISTNAME = yosys-0.9pl4081
-REVISION = 4
+COMMENT= Yosys Open SYnthesis Suite
+CATEGORIES= cad
+V= 0.66pl20260626
+DISTNAME= yosys-${V}
-GH_ACCOUNT = YosysHQ
-GH_PROJECT = yosys
-GH_COMMIT = 25de8faf10157ab0cb40f77c7cbf3143527c598e
+GH_ACCOUNT= YosysHQ
+GH_PROJECT= yosys
+GH_COMMIT= f624bcf2db6275d2d1022e6bd755be17221563a6
-CATEGORIES = cad
-HOMEPAGE = http://www.clifford.at/yosys/
-MAINTAINER = Alessandro De Laurenzis <just22@atlantide.mooo.com>
+DIST_TUPLE+= github jarro2783 cxxopts v3.2.1 libs/cxxopts/
+DIST_TUPLE+= github YosysHQ abc v0.65 abc/
-# ISC (yosys), MIT (MiniSat)
-PERMIT_PACKAGE = Yes
+HOMEPAGE= https://github.com/YosysHQ
+MAINTAINER= Thomas Dettbarn <dettus@dettus.net>
-WANTLIB += ${COMPILER_LIBCXX} ${MODTCL_WANTLIB} c m readline ffi z
+# ISC license
+PERMIT_PACKAGE= Yes
-# C++11
-COMPILER = base-clang ports-gcc
+WANTLIB= c ${COMPILER_LIBCXX} m z ffi
-MODULES = lang/python \
- lang/tcl
+MODULES= devel/cmake
+NO_TEST= Yes
-CONFIGURE_STYLE = none
-
-BUILD_DEPENDS = devel/bison \
- shells/bash
-
-RUN_DEPENDS = cad/abc \
- math/graphviz \
- graphics/xdot \
- shells/bash
-
-LIB_DEPENDS = ${MODTCL_LIB_DEPENDS} \
- devel/libffi
-
-TEST_DEPENDS = ${BUILD_PKGPATH} \
- cad/abc \
- lang/gawk \
- lang/iverilog \
- shells/bash
-
-USE_GMAKE = Yes
-
-MAKE_FLAGS = CXX="${CXX}" \
- LD="${CXX} -L${LOCALBASE}/lib" \
- PRETTY=0
-
-MAKE_ENV = ABCEXTERNAL=${LOCALBASE}/bin/abc \
- CXXFLAGS="${CXXFLAGS}" \
- TCL_VERSION="${MODTCL_LIB}" \
- TCL_INCLUDE="${MODTCL_INCDIR}"
-
-TEST_ENV = MAKE="${MAKE_PROGRAM}"
-
-FAKE_FLAGS = PREFIX="${TRUEPREFIX}"
-
-# the only gcc-specific things from "config-gcc" are setting CXX/LD, which
-# we override above
-do-configure:
- @${SUBST_CMD} ${WRKSRC}/kernel/yosys.cc
- @cd ${WRKBUILD} && exec env -i ${MAKE_ENV} ${MAKE_PROGRAM} config-gcc
-
-post-build:
- grep -rl "#!/bin/bash" ${WRKSRC} | \
- xargs sed -i 's,#!/bin/bash,#!${LOCALBASE}/bin/bash,'
-
-post-install:
- ${MODPY_COMPILEALL} ${PREFIX}/share/yosys/python3
+LIB_DEPENDS= devel/libffi
+BUILD_DEPENDS= devel/bison
.include <bsd.port.mk>
+
diff --git a/cad/yosys/distinfo b/cad/yosys/distinfo
index 97997594a63..19b278e5a80 100644
--- a/cad/yosys/distinfo
+++ b/cad/yosys/distinfo
@@ -1,2 +1,6 @@
-SHA256 (yosys-0.9pl4081-25de8faf.tar.gz) = ProWZDm6xHgXlv8M1zJn+b4zrgGUIUpap6YV5MrdKRM=
-SIZE (yosys-0.9pl4081-25de8faf.tar.gz) = 1976189
+SHA256 (YosysHQ-abc-v0.65.tar.gz) = JD9SmxFVv3nNnq21DoJadG/1lfvKaGinS6I1iDKTyNk=
+SHA256 (jarro2783-cxxopts-v3.2.1.tar.gz) = hB9J8uBFucY2WZfCqPv3bm8hUELdpFEaW7BLxevH+Io=
+SHA256 (yosys-0.66pl20260626-f624bcf2.tar.gz) = D8FPmPnes0zxWl5udD+nRjJiQaTTJ+s48jfsShOKh7E=
+SIZE (YosysHQ-abc-v0.65.tar.gz) = 7387477
+SIZE (jarro2783-cxxopts-v3.2.1.tar.gz) = 160606
+SIZE (yosys-0.66pl20260626-f624bcf2.tar.gz) = 3671894
diff --git a/cad/yosys/pkg/DESCR b/cad/yosys/pkg/DESCR
index 02b6e734fdc..f5cf4b125f0 100644
--- a/cad/yosys/pkg/DESCR
+++ b/cad/yosys/pkg/DESCR
@@ -1,16 +1,15 @@
-Yosys Open SYnthesis Suite
+This is a framework for RTL synthesis tools. It currently has extensive
+Verilog-2005 support and provides a basic set of synthesis algorithms for
+various application domains.
-Yosys is a framework for Verilog RTL synthesis. It currently has extensive
-Verilog-2005 support and provides a basic set of synthesis algorithms for
-various application domains. Selected features and typical applications:
+Yosys can be adapted to perform any synthesis job by combining the existing
+passes (algorithms) using synthesis scripts and adding additional passes as
+needed by extending the yosys C++ code base.
-- Process almost any synthesizable Verilog-2005 design
-- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
-- Built-in formal methods for checking properties and equivalence
-- Mapping to ASIC standard cell libraries (in Liberty File Format)
-- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
-- Foundation and/or front-end for custom flows
+Yosys is free software licensed under the ISC license (a GPL compatible
+license that is similar in terms to the MIT license or the 2-clause BSD
+license).
-Yosys can be adapted to perform any synthesis job by combining the existing
-passes (algorithms) using synthesis scripts and adding additional passes as
-needed by extending the Yosys C++ code base.
+Third-party software distributed alongside this software is licensed under
+compatible licenses. Please refer to abc and libs subdirectories for their
+license terms.
diff --git a/cad/yosys/pkg/PLIST b/cad/yosys/pkg/PLIST
index ba3bdfd5693..543fae8ae58 100644
--- a/cad/yosys/pkg/PLIST
+++ b/cad/yosys/pkg/PLIST
@@ -1,7 +1,10 @@
@bin bin/yosys
+@bin bin/yosys-abc
bin/yosys-config
@bin bin/yosys-filterlib
bin/yosys-smtbmc
+bin/yosys-witness
+share/doc/pkg-readmes/${PKGSTEM}
share/yosys/
share/yosys/abc9_map.v
share/yosys/abc9_model.v
@@ -11,17 +14,36 @@ share/yosys/achronix/speedster22i/
share/yosys/achronix/speedster22i/cells_map.v
share/yosys/achronix/speedster22i/cells_sim.v
share/yosys/adff2dff.v
+share/yosys/analogdevices/
+share/yosys/analogdevices/abc9_model.v
+share/yosys/analogdevices/arith_map.v
+share/yosys/analogdevices/brams.txt
+share/yosys/analogdevices/brams_defs.vh
+share/yosys/analogdevices/brams_map.v
+share/yosys/analogdevices/cells_map.v
+share/yosys/analogdevices/cells_sim.v
+share/yosys/analogdevices/dsp_map.v
+share/yosys/analogdevices/ff_map.v
+share/yosys/analogdevices/lut_map.v
+share/yosys/analogdevices/lutrams.txt
+share/yosys/analogdevices/lutrams_map.v
+share/yosys/analogdevices/mux_map.v
share/yosys/anlogic/
share/yosys/anlogic/arith_map.v
+share/yosys/anlogic/brams.txt
+share/yosys/anlogic/brams_map.v
share/yosys/anlogic/cells_map.v
share/yosys/anlogic/cells_sim.v
share/yosys/anlogic/eagle_bb.v
-share/yosys/anlogic/lutram_init_16x4.vh
share/yosys/anlogic/lutrams.txt
share/yosys/anlogic/lutrams_map.v
-share/yosys/cells.lib
+share/yosys/choices/
+share/yosys/choices/han-carlson.v
+share/yosys/choices/kogge-stone.v
+share/yosys/choices/sklansky.v
share/yosys/cmp2lcu.v
share/yosys/cmp2lut.v
+share/yosys/cmp2softlogic.v
share/yosys/coolrunner2/
share/yosys/coolrunner2/cells_counter_map.v
share/yosys/coolrunner2/cells_latch.v
@@ -30,26 +52,12 @@ share/yosys/coolrunner2/tff_extract.v
share/yosys/coolrunner2/xc2_dff.lib
share/yosys/dff2ff.v
share/yosys/ecp5/
-share/yosys/ecp5/arith_map.v
-share/yosys/ecp5/bram_conn_1.vh
-share/yosys/ecp5/bram_conn_18.vh
-share/yosys/ecp5/bram_conn_2.vh
-share/yosys/ecp5/bram_conn_36.vh
-share/yosys/ecp5/bram_conn_4.vh
-share/yosys/ecp5/bram_conn_9.vh
-share/yosys/ecp5/bram_init_1_2_4.vh
-share/yosys/ecp5/bram_init_9_18_36.vh
-share/yosys/ecp5/brams.txt
-share/yosys/ecp5/brams_map.v
+share/yosys/ecp5/ccu2c_sim.vh
share/yosys/ecp5/cells_bb.v
share/yosys/ecp5/cells_ff.vh
share/yosys/ecp5/cells_io.vh
-share/yosys/ecp5/cells_map.v
share/yosys/ecp5/cells_sim.v
-share/yosys/ecp5/dsp_map.v
-share/yosys/ecp5/latches_map.v
-share/yosys/ecp5/lutrams.txt
-share/yosys/ecp5/lutrams_map.v
+share/yosys/ecp5/common_sim.vh
share/yosys/efinix/
share/yosys/efinix/arith_map.v
share/yosys/efinix/brams.txt
@@ -57,15 +65,43 @@ share/yosys/efinix/brams_map.v
share/yosys/efinix/cells_map.v
share/yosys/efinix/cells_sim.v
share/yosys/efinix/gbuf_map.v
+share/yosys/fabulous/
+share/yosys/fabulous/arith_map.v
+share/yosys/fabulous/cells_map.v
+share/yosys/fabulous/ff_map.v
+share/yosys/fabulous/io_map.v
+share/yosys/fabulous/latches_map.v
+share/yosys/fabulous/prims.v
+share/yosys/fabulous/ram_regfile.txt
+share/yosys/fabulous/regfile_map.v
share/yosys/gate2lut.v
+share/yosys/gatemate/
+share/yosys/gatemate/arith_map.v
+share/yosys/gatemate/brams.txt
+share/yosys/gatemate/brams_init_20.vh
+share/yosys/gatemate/brams_init_40.vh
+share/yosys/gatemate/brams_map.v
+share/yosys/gatemate/cells_bb.v
+share/yosys/gatemate/cells_sim.v
+share/yosys/gatemate/inv_map.v
+share/yosys/gatemate/lut_map.v
+share/yosys/gatemate/lut_tree_cells.genlib
+share/yosys/gatemate/lut_tree_map.v
+share/yosys/gatemate/mul_map.v
+share/yosys/gatemate/mux_map.v
+share/yosys/gatemate/reg_map.v
share/yosys/gowin/
share/yosys/gowin/arith_map.v
-share/yosys/gowin/bram_init_16.vh
share/yosys/gowin/brams.txt
-share/yosys/gowin/brams_init3.vh
share/yosys/gowin/brams_map.v
+share/yosys/gowin/brams_map_gw5a.v
+share/yosys/gowin/cells_latch.v
share/yosys/gowin/cells_map.v
share/yosys/gowin/cells_sim.v
+share/yosys/gowin/cells_xtra_gw1n.v
+share/yosys/gowin/cells_xtra_gw2a.v
+share/yosys/gowin/cells_xtra_gw5a.v
+share/yosys/gowin/dsp_map.v
share/yosys/gowin/lutrams.txt
share/yosys/gowin/lutrams_map.v
share/yosys/greenpak4/
@@ -81,51 +117,79 @@ share/yosys/ice40/
share/yosys/ice40/abc9_model.v
share/yosys/ice40/arith_map.v
share/yosys/ice40/brams.txt
-share/yosys/ice40/brams_init1.vh
-share/yosys/ice40/brams_init2.vh
-share/yosys/ice40/brams_init3.vh
share/yosys/ice40/brams_map.v
share/yosys/ice40/cells_map.v
share/yosys/ice40/cells_sim.v
share/yosys/ice40/dsp_map.v
share/yosys/ice40/ff_map.v
share/yosys/ice40/latches_map.v
+share/yosys/ice40/spram.txt
+share/yosys/ice40/spram_map.v
share/yosys/include/
share/yosys/include/backends/
share/yosys/include/backends/cxxrtl/
-share/yosys/include/backends/cxxrtl/cxxrtl.h
-share/yosys/include/backends/cxxrtl/cxxrtl_capi.cc
-share/yosys/include/backends/cxxrtl/cxxrtl_capi.h
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd.h
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.h
+share/yosys/include/backends/cxxrtl/runtime/
+share/yosys/include/backends/cxxrtl/runtime/README.txt
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
share/yosys/include/backends/rtlil/
share/yosys/include/backends/rtlil/rtlil_backend.h
share/yosys/include/frontends/
-share/yosys/include/frontends/ast/
-share/yosys/include/frontends/ast/ast.h
+share/yosys/include/frontends/blif/
+share/yosys/include/frontends/blif/blifparse.h
share/yosys/include/kernel/
+share/yosys/include/kernel/binding.h
+share/yosys/include/kernel/bitpattern.h
+share/yosys/include/kernel/cellaigs.h
share/yosys/include/kernel/celledges.h
share/yosys/include/kernel/celltypes.h
share/yosys/include/kernel/consteval.h
share/yosys/include/kernel/constids.inc
+share/yosys/include/kernel/cost.h
+share/yosys/include/kernel/drivertools.h
share/yosys/include/kernel/ff.h
share/yosys/include/kernel/ffinit.h
+share/yosys/include/kernel/ffmerge.h
+share/yosys/include/kernel/fmt.h
+share/yosys/include/kernel/fstdata.h
+share/yosys/include/kernel/gzip.h
share/yosys/include/kernel/hashlib.h
+share/yosys/include/kernel/io.h
+share/yosys/include/kernel/json.h
share/yosys/include/kernel/log.h
share/yosys/include/kernel/macc.h
share/yosys/include/kernel/mem.h
share/yosys/include/kernel/modtools.h
+share/yosys/include/kernel/newcelltypes.h
+share/yosys/include/kernel/qcsat.h
share/yosys/include/kernel/register.h
share/yosys/include/kernel/rtlil.h
share/yosys/include/kernel/satgen.h
+share/yosys/include/kernel/scopeinfo.h
+share/yosys/include/kernel/sexpr.h
share/yosys/include/kernel/sigtools.h
+share/yosys/include/kernel/threading.h
+share/yosys/include/kernel/timinginfo.h
share/yosys/include/kernel/utils.h
share/yosys/include/kernel/yosys.h
+share/yosys/include/kernel/yosys_common.h
+share/yosys/include/kernel/yosys_config.h
+share/yosys/include/kernel/yw.h
share/yosys/include/libs/
share/yosys/include/libs/ezsat/
+share/yosys/include/libs/ezsat/ezcmdline.h
share/yosys/include/libs/ezsat/ezminisat.h
share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/fst/
+share/yosys/include/libs/fst/fstapi.h
share/yosys/include/libs/json11/
share/yosys/include/libs/json11/json11.hpp
share/yosys/include/libs/sha1/
@@ -133,6 +197,8 @@ share/yosys/include/libs/sha1/sha1.h
share/yosys/include/passes/
share/yosys/include/passes/fsm/
share/yosys/include/passes/fsm/fsmdata.h
+share/yosys/include/passes/techmap/
+share/yosys/include/passes/techmap/libparse.h
share/yosys/intel/
share/yosys/intel/common/
share/yosys/intel/common/altpll_bb.v
@@ -152,6 +218,7 @@ share/yosys/intel/cycloneive/cells_sim.v
share/yosys/intel/max10/
share/yosys/intel/max10/cells_map.v
share/yosys/intel/max10/cells_sim.v
+share/yosys/intel/max10/dsp_map.v
share/yosys/intel_alm/
share/yosys/intel_alm/common/
share/yosys/intel_alm/common/abc9_map.v
@@ -161,8 +228,7 @@ share/yosys/intel_alm/common/alm_map.v
share/yosys/intel_alm/common/alm_sim.v
share/yosys/intel_alm/common/arith_alm_map.v
share/yosys/intel_alm/common/bram_m10k.txt
-share/yosys/intel_alm/common/bram_m20k.txt
-share/yosys/intel_alm/common/bram_m20k_map.v
+share/yosys/intel_alm/common/bram_m10k_map.v
share/yosys/intel_alm/common/dff_map.v
share/yosys/intel_alm/common/dff_sim.v
share/yosys/intel_alm/common/dsp_map.v
@@ -171,86 +237,160 @@ share/yosys/intel_alm/common/lutram_mlab.txt
share/yosys/intel_alm/common/megafunction_bb.v
share/yosys/intel_alm/common/mem_sim.v
share/yosys/intel_alm/common/misc_sim.v
-share/yosys/intel_alm/common/quartus_rename.v
share/yosys/intel_alm/cyclonev/
share/yosys/intel_alm/cyclonev/cells_sim.v
-share/yosys/machxo2/
-share/yosys/machxo2/cells_map.v
-share/yosys/machxo2/cells_sim.v
+share/yosys/lattice/
+share/yosys/lattice/arith_map_ccu2c.v
+share/yosys/lattice/arith_map_ccu2d.v
+share/yosys/lattice/arith_map_nexus.v
+share/yosys/lattice/brams_16kd.txt
+share/yosys/lattice/brams_8kc.txt
+share/yosys/lattice/brams_map_16kd.v
+share/yosys/lattice/brams_map_8kc.v
+share/yosys/lattice/brams_map_nexus.v
+share/yosys/lattice/brams_nexus.txt
+share/yosys/lattice/ccu2c_sim.vh
+share/yosys/lattice/ccu2d_sim.vh
+share/yosys/lattice/cells_bb_ecp5.v
+share/yosys/lattice/cells_bb_nexus.v
+share/yosys/lattice/cells_bb_xo2.v
+share/yosys/lattice/cells_bb_xo3.v
+share/yosys/lattice/cells_bb_xo3d.v
+share/yosys/lattice/cells_ff.vh
+share/yosys/lattice/cells_io.vh
+share/yosys/lattice/cells_map_nexus.v
+share/yosys/lattice/cells_map_trellis.v
+share/yosys/lattice/cells_sim_ecp5.v
+share/yosys/lattice/cells_sim_nexus.v
+share/yosys/lattice/cells_sim_xo2.v
+share/yosys/lattice/cells_sim_xo3.v
+share/yosys/lattice/cells_sim_xo3d.v
+share/yosys/lattice/common_sim.vh
+share/yosys/lattice/dsp_map_18x18.v
+share/yosys/lattice/dsp_map_nexus.v
+share/yosys/lattice/latches_map.v
+share/yosys/lattice/lrams_map_nexus.v
+share/yosys/lattice/lrams_nexus.txt
+share/yosys/lattice/lutrams_map_nexus.v
+share/yosys/lattice/lutrams_map_trellis.v
+share/yosys/lattice/lutrams_nexus.txt
+share/yosys/lattice/lutrams_trellis.txt
+share/yosys/lattice/parse_init.vh
+share/yosys/microchip/
+share/yosys/microchip/LSRAM.txt
+share/yosys/microchip/LSRAM_map.v
+share/yosys/microchip/arith_map.v
+share/yosys/microchip/brams_defs.vh
+share/yosys/microchip/cells_map.v
+share/yosys/microchip/cells_sim.v
+share/yosys/microchip/polarfire_dsp_map.v
+share/yosys/microchip/uSRAM.txt
+share/yosys/microchip/uSRAM_map.v
share/yosys/mul2dsp.v
+share/yosys/nanoxplore/
+share/yosys/nanoxplore/arith_map.v
+share/yosys/nanoxplore/brams.txt
+share/yosys/nanoxplore/brams_init.vh
+share/yosys/nanoxplore/brams_map.v
+share/yosys/nanoxplore/cells_bb.v
+share/yosys/nanoxplore/cells_bb_l.v
+share/yosys/nanoxplore/cells_bb_m.v
+share/yosys/nanoxplore/cells_bb_u.v
+share/yosys/nanoxplore/cells_map.v
+share/yosys/nanoxplore/cells_sim.v
+share/yosys/nanoxplore/cells_sim_l.v
+share/yosys/nanoxplore/cells_sim_m.v
+share/yosys/nanoxplore/cells_sim_u.v
+share/yosys/nanoxplore/cells_wrap.v
+share/yosys/nanoxplore/cells_wrap_l.v
+share/yosys/nanoxplore/cells_wrap_m.v
+share/yosys/nanoxplore/cells_wrap_u.v
+share/yosys/nanoxplore/io_map.v
+share/yosys/nanoxplore/latches_map.v
+share/yosys/nanoxplore/rf_init.vh
+share/yosys/nanoxplore/rf_rams_l.txt
+share/yosys/nanoxplore/rf_rams_m.txt
+share/yosys/nanoxplore/rf_rams_map_l.v
+share/yosys/nanoxplore/rf_rams_map_m.v
+share/yosys/nanoxplore/rf_rams_map_u.v
+share/yosys/nanoxplore/rf_rams_u.txt
share/yosys/nexus/
-share/yosys/nexus/arith_map.v
-share/yosys/nexus/brams.txt
-share/yosys/nexus/brams_init.vh
-share/yosys/nexus/brams_map.v
-share/yosys/nexus/cells_map.v
share/yosys/nexus/cells_sim.v
share/yosys/nexus/cells_xtra.v
-share/yosys/nexus/dsp_map.v
-share/yosys/nexus/latches_map.v
-share/yosys/nexus/lrams.txt
-share/yosys/nexus/lrams_init.vh
-share/yosys/nexus/lrams_map.v
-share/yosys/nexus/lutrams.txt
-share/yosys/nexus/lutrams_map.v
share/yosys/nexus/parse_init.vh
share/yosys/pmux2mux.v
share/yosys/python3/
-share/yosys/python3/${MODPY_PYCACHE}/
-share/yosys/python3/${MODPY_PYCACHE}smtio.${MODPY_PYC_MAGIC_TAG}${MODPY_PYOEXTENSION}
-share/yosys/python3/${MODPY_PYCACHE}smtio.${MODPY_PYC_MAGIC_TAG}pyc
share/yosys/python3/smtio.py
+share/yosys/python3/ywio.py
share/yosys/quicklogic/
-share/yosys/quicklogic/abc9_map.v
-share/yosys/quicklogic/abc9_model.v
-share/yosys/quicklogic/abc9_unmap.v
-share/yosys/quicklogic/cells_sim.v
-share/yosys/quicklogic/lut_sim.v
-share/yosys/quicklogic/pp3_cells_map.v
-share/yosys/quicklogic/pp3_cells_sim.v
-share/yosys/quicklogic/pp3_ffs_map.v
-share/yosys/quicklogic/pp3_latches_map.v
-share/yosys/quicklogic/pp3_lut_map.v
+share/yosys/quicklogic/common/
+share/yosys/quicklogic/common/cells_sim.v
+share/yosys/quicklogic/pp3/
+share/yosys/quicklogic/pp3/abc9_map.v
+share/yosys/quicklogic/pp3/abc9_model.v
+share/yosys/quicklogic/pp3/abc9_unmap.v
+share/yosys/quicklogic/pp3/cells_map.v
+share/yosys/quicklogic/pp3/cells_sim.v
+share/yosys/quicklogic/pp3/ffs_map.v
+share/yosys/quicklogic/pp3/latches_map.v
+share/yosys/quicklogic/pp3/lut_map.v
+share/yosys/quicklogic/qlf_k6n10f/
+share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+share/yosys/quicklogic/qlf_k6n10f/arith_map.v
+share/yosys/quicklogic/qlf_k6n10f/bram_types_sim.v
+share/yosys/quicklogic/qlf_k6n10f/brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
+share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
+share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams.txt
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/sram1024x18_mem.v
+share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
+share/yosys/sdc/
+share/yosys/sdc/graph-stubs.sdc
share/yosys/sf2/
share/yosys/sf2/arith_map.v
share/yosys/sf2/cells_map.v
share/yosys/sf2/cells_sim.v
share/yosys/simcells.v
share/yosys/simlib.v
+share/yosys/smtmap.v
share/yosys/techmap.v
share/yosys/xilinx/
share/yosys/xilinx/abc9_model.v
share/yosys/xilinx/arith_map.v
-share/yosys/xilinx/brams_init_16.vh
-share/yosys/xilinx/brams_init_18.vh
-share/yosys/xilinx/brams_init_32.vh
-share/yosys/xilinx/brams_init_36.vh
-share/yosys/xilinx/brams_init_8.vh
-share/yosys/xilinx/brams_init_9.vh
+share/yosys/xilinx/brams_defs.vh
+share/yosys/xilinx/brams_xc2v.txt
+share/yosys/xilinx/brams_xc2v_map.v
+share/yosys/xilinx/brams_xc3sda.txt
+share/yosys/xilinx/brams_xc3sda_map.v
+share/yosys/xilinx/brams_xc4v.txt
+share/yosys/xilinx/brams_xc4v_map.v
+share/yosys/xilinx/brams_xc5v_map.v
+share/yosys/xilinx/brams_xc6v_map.v
+share/yosys/xilinx/brams_xcu_map.v
+share/yosys/xilinx/brams_xcv.txt
+share/yosys/xilinx/brams_xcv_map.v
share/yosys/xilinx/cells_map.v
share/yosys/xilinx/cells_sim.v
share/yosys/xilinx/cells_xtra.v
share/yosys/xilinx/ff_map.v
-share/yosys/xilinx/lut4_lutrams.txt
-share/yosys/xilinx/lut6_lutrams.txt
share/yosys/xilinx/lut_map.v
-share/yosys/xilinx/lutrams_map.v
+share/yosys/xilinx/lutrams_xc5v.txt
+share/yosys/xilinx/lutrams_xc5v_map.v
+share/yosys/xilinx/lutrams_xcu.txt
+share/yosys/xilinx/lutrams_xcv.txt
+share/yosys/xilinx/lutrams_xcv_map.v
share/yosys/xilinx/mux_map.v
-share/yosys/xilinx/xc2v_brams.txt
-share/yosys/xilinx/xc2v_brams_map.v
+share/yosys/xilinx/urams.txt
+share/yosys/xilinx/urams_map.v
share/yosys/xilinx/xc3s_mult_map.v
-share/yosys/xilinx/xc3sa_brams.txt
-share/yosys/xilinx/xc3sda_brams.txt
share/yosys/xilinx/xc3sda_dsp_map.v
share/yosys/xilinx/xc4v_dsp_map.v
share/yosys/xilinx/xc5v_dsp_map.v
-share/yosys/xilinx/xc6s_brams.txt
-share/yosys/xilinx/xc6s_brams_map.v
share/yosys/xilinx/xc6s_dsp_map.v
-share/yosys/xilinx/xc7_brams_map.v
share/yosys/xilinx/xc7_dsp_map.v
-share/yosys/xilinx/xc7_xcu_brams.txt
-share/yosys/xilinx/xcu_brams_map.v
share/yosys/xilinx/xcu_dsp_map.v
-share/yosys/xilinx/xcup_urams.txt
-share/yosys/xilinx/xcup_urams_map.v
diff --git a/cad/yosys/patches/patch-CMakeLists_txt b/cad/yosys/patches/patch-CMakeLists_txt
new file mode 100644
index 00000000000..d8886a1eda8
--- /dev/null
+++ b/cad/yosys/patches/patch-CMakeLists_txt
@@ -0,0 +1,13 @@
+Build check failed because of wrong flex version number.
+Index: CMakeLists.txt
+--- CMakeLists.txt.orig
++++ CMakeLists.txt
+@@ -172,7 +172,7 @@ if (APPLE)
+ use_homebrew()
+ endif()
+
+-find_package(FLEX 2.6)
++find_package(FLEX 2.5.39)
+ set_package_properties(FLEX PROPERTIES
+ URL "https://github.com/westes/flex"
+ DESCRIPTION "The Fast Lexical Analyzer"
diff --git a/cad/yosys/patches/patch-Makefile b/cad/yosys/patches/patch-Makefile
deleted file mode 100644
index b18023bc8a3..00000000000
--- a/cad/yosys/patches/patch-Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-Index: Makefile
---- Makefile.orig
-+++ Makefile
-@@ -85,7 +85,7 @@ all: top-all
- YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
- VPATH := $(YOSYS_SRC)
-
--CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
-+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
- LDLIBS := $(LDLIBS) -lstdc++ -lm
- PLUGIN_LDFLAGS :=
-
-@@ -349,6 +349,10 @@ else ifneq ($(CONFIG),none)
- $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2-32, msys2-64)
- endif
-
-+ifeq ($(OS), OpenBSD)
-+LDLIBS := $(filter-out -lrt, $(LDLIBS))
-+endif
-+
- ifeq ($(ENABLE_LIBYOSYS),1)
- TARGETS += libyosys.so
- endif
-@@ -439,7 +443,7 @@ endif
- ifeq ($(ENABLE_PLUGINS),1)
- CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags libffi) -DYOSYS_ENABLE_PLUGINS
- LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs libffi || echo -lffi)
--ifneq ($(OS), FreeBSD)
-+ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD))
- LDLIBS += -ldl
- endif
- endif
diff --git a/cad/yosys/patches/patch-cmake_FindBISON_cmake b/cad/yosys/patches/patch-cmake_FindBISON_cmake
new file mode 100644
index 00000000000..f0e46bba943
--- /dev/null
+++ b/cad/yosys/patches/patch-cmake_FindBISON_cmake
@@ -0,0 +1,13 @@
+The resulting environment variable was broken
+Index: cmake/FindBISON.cmake
+--- cmake/FindBISON.cmake.orig
++++ cmake/FindBISON.cmake
+@@ -315,7 +315,7 @@ if(BISON_EXECUTABLE)
+ unset(_BISON_CMP0088)
+
+ add_custom_command(OUTPUT ${BISON_TARGET_outputs}
+- COMMAND ${CMAKE_COMMAND} -E env "M4=${BISON_M4_EXECUTABLE}"
++ COMMAND ${CMAKE_COMMAND} -E env
+ ${BISON_EXECUTABLE} ${BISON_TARGET_cmdopt} -o ${BisonOutput} ${_BisonInput}
+ VERBATIM
+ DEPENDS ${_BisonInput}
diff --git a/cad/yosys/patches/patch-kernel_yosys_cc b/cad/yosys/patches/patch-kernel_yosys_cc
deleted file mode 100644
index f929a46a7f8..00000000000
--- a/cad/yosys/patches/patch-kernel_yosys_cc
+++ /dev/null
@@ -1,26 +0,0 @@
-Index: kernel/yosys.cc
---- kernel/yosys.cc.orig
-+++ kernel/yosys.cc
-@@ -69,6 +69,10 @@
- #endif
- #endif
-
-+#ifdef __OpenBSD__
-+# include <sys/wait.h>
-+#endif
-+
- #include <limits.h>
- #include <errno.h>
-
-@@ -787,6 +791,11 @@ std::string proc_self_dirname()
- path.assign(buffer, buflen);
- free(buffer);
- return path;
-+}
-+#elif defined(__OpenBSD__)
-+std::string proc_self_dirname()
-+{
-+ return "${PREFIX}/bin/";
- }
- #elif defined(__APPLE__)
- std::string proc_self_dirname()
diff --git a/cad/yosys/patches/patch-passes_cmds_show_cc b/cad/yosys/patches/patch-passes_cmds_show_cc
deleted file mode 100644
index e7a9b5a12e2..00000000000
--- a/cad/yosys/patches/patch-passes_cmds_show_cc
+++ /dev/null
@@ -1,12 +0,0 @@
-Index: passes/cmds/show.cc
---- passes/cmds/show.cc.orig
-+++ passes/cmds/show.cc
-@@ -880,7 +880,7 @@ struct ShowPass : public Pass {
- #ifdef __APPLE__
- std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
- #else
-- std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
-+ std::string cmd = stringf("test -f '%s.pid' -a -n \"`fuser '%s.pid' 2>/dev/null`\" || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
- #endif
- log("Exec: %s\n", cmd.c_str());
- if (run_command(cmd) != 0)
diff --git a/cad/yosys/pkg/README b/cad/yosys/pkg/README
new file mode 100644
index 00000000000..58af3a83bb1
--- /dev/null
+++ b/cad/yosys/pkg/README
@@ -0,0 +1,23 @@
++-------------------------------------------------------------------------------
+| Running ${PKGSTEM} on OpenBSD
++-------------------------------------------------------------------------------
+
+High RAM consumption
+====================
+
+Synthesizing FPGAs is a memory intensive task. Even relatively small designs
+might lead to errors such as
+
+ libc++abi: terminating due to uncaught exception of type std::bad_alloc
+ Abort trap (core dumped)
+
+In this case, editing /etc/login.conf(5), to increase the parameters
+
+ default:\
+ datasize-max=8192M:\
+ datasize-cur=8192M
+
+helps. Obviously, it is required to log off and on again, before it has any
+effect on re-running YoSys.
+
+
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