llvm: garbage-collect local changes for now-retired loongson platform

We have been carrying along some local LLVM fix for loongson that can now be dropped. BTW, I'm pretty sure the change to clang/lib/Driver/ToolChains/Clang.cpp has been mismerged. I don't know if this affects the build on other platforms. I've bumped REVISION, and I intend to test build llvm/22 on amd64 once I have some free cycles. I have sent a corresponding patch for base to tech@. ----------------------------------------------- commit 00c891c247b8c4b1e003736c2959d74c3408299c (mystuff) from: Christian Weisgerber <naddy@mips.inka.de> date: Thu Jul 16 22:35:09 2026 UTC llvm: garbage-collect local changes for now-retired loongson platform M devel/clang-tools-extra/Makefile M devel/clang-tools-extra/patches/patch-clang_include_clang_Options_Options_td M devel/clang-tools-extra/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp D devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp M devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt D devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp D devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp D devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp D devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_Mips_h M devel/llvm/19/Makefile M devel/llvm/19/patches/patch-clang_include_clang_Driver_Options_td M devel/llvm/19/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp D devel/llvm/19/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp M devel/llvm/19/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt D devel/llvm/19/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp D devel/llvm/19/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp D devel/llvm/19/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp D devel/llvm/19/patches/patch-llvm_lib_Target_Mips_Mips_h M devel/llvm/20/Makefile M devel/llvm/20/patches/patch-clang_include_clang_Driver_Options_td M devel/llvm/20/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp D devel/llvm/20/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp M devel/llvm/20/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt D devel/llvm/20/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp D devel/llvm/20/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp D devel/llvm/20/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp D devel/llvm/20/patches/patch-llvm_lib_Target_Mips_Mips_h M devel/llvm/21/Makefile M devel/llvm/21/patches/patch-clang_include_clang_Driver_Options_td M devel/llvm/21/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp D devel/llvm/21/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp M devel/llvm/21/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt D devel/llvm/21/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp D devel/llvm/21/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp D devel/llvm/21/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp D devel/llvm/21/patches/patch-llvm_lib_Target_Mips_Mips_h M devel/llvm/22/Makefile M devel/llvm/22/patches/patch-clang_include_clang_Options_Options_td M devel/llvm/22/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp D devel/llvm/22/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp M devel/llvm/22/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt D devel/llvm/22/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp D devel/llvm/22/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp D devel/llvm/22/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp D devel/llvm/22/patches/patch-llvm_lib_Target_Mips_Mips_h diff 96ae8a25eba6ef4aff1dd1bf92e487b2298b10c2 00c891c247b8c4b1e003736c2959d74c3408299c commit - 96ae8a25eba6ef4aff1dd1bf92e487b2298b10c2 commit + 00c891c247b8c4b1e003736c2959d74c3408299c blob - 74660973b137749b20f9dc32405f2a27ec977798 blob + 5f42a423aa5a5b42766fd4b74d10bae730736e0f --- devel/clang-tools-extra/Makefile +++ devel/clang-tools-extra/Makefile @@ -13,7 +13,7 @@ DPB_PROPERTIES = parallel COMMENT= Clang extra tools LLVM_V = 22.1.6 -REVISION = 0 +REVISION = 1 DISTNAME = llvm-project-${LLVM_V}.src PKGNAME= clang-tools-extra-${LLVM_V} blob - cacef63a8679267b7edf2b8f7a9652d4fb9cd4e3 blob + 073d246881aacd1101ff9a67b46f6c5846591103 --- devel/clang-tools-extra/patches/patch-clang_include_clang_Options_Options_td +++ devel/clang-tools-extra/patches/patch-clang_include_clang_Options_Options_td @@ -22,16 +22,7 @@ Index: clang/include/clang/Options/Options.td def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-stop-after=">, Group<f_Group>, Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">, -@@ -5912,6 +5926,8 @@ def mno_check_zero_division : Flag<["-"], "mno-check-z - def mfix4300 : Flag<["-"], "mfix4300">, Group<m_mips_Features_Group>; - def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, - Group<m_mips_Features_Group>; -+def mfix_loongson2f_btb : Flag<["-"], "mfix-loongson2f-btb">, -+ Group<m_mips_Features_Group>; - } // let Flags = [TargetSpecific] - def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>, - IgnoredGCCCompat; -@@ -6154,10 +6170,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro +@@ -6154,10 +6168,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro def pedantic : Flag<["-", "--"], "pedantic">, Group<pedantic_Group>, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Warn on language extensions">, MarshallingInfoFlag<DiagnosticOpts<"Pedantic">>; @@ -47,7 +38,7 @@ Index: clang/include/clang/Options/Options.td def pipe : Flag<["-", "--"], "pipe">, HelpText<"Use pipes between commands, when possible">; def prebind__all__twolevel__modules : Flag<["-"], "prebind_all_twolevel_modules">; -@@ -7007,6 +7027,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur +@@ -7007,6 +7025,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>; def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>; def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>; blob - 7a9114adfcdeacf412035d04c2a1ca587a9a6e69 blob + 75ca5ab5bb5b5db8becaf85972e54a4857c549f7 --- devel/clang-tools-extra/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp +++ devel/clang-tools-extra/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp @@ -1,19 +1,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp --- clang/lib/Driver/ToolChains/Clang.cpp.orig +++ clang/lib/Driver/ToolChains/Clang.cpp -@@ -3044,6 +3044,11 @@ static void RenderFloatingPointOptions(const ToolChain - << LastFpContractOverrideOption - << Args.MakeArgString("-ffp-contract=" + Val); - } -+ if (Val.starts_with("-mfix-loongson2f-btb")) { -+ CmdArgs.push_back("-mllvm"); -+ CmdArgs.push_back("-fix-loongson2f-btb"); -+ continue; -+ } - - FPContract = Val; - LastSeenFfpContractOption = Val; -@@ -5807,9 +5812,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -5807,9 +5807,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi OFastEnabled ? options::OPT_Ofast : options::OPT_fstrict_aliasing; // We turn strict aliasing off by default if we're Windows MSVC since MSVC // doesn't do any TBAA. @@ -28,7 +16,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp CmdArgs.push_back("-relaxed-aliasing"); if (Args.hasFlag(options::OPT_fno_pointer_tbaa, options::OPT_fpointer_tbaa, false)) -@@ -6918,7 +6926,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -6918,7 +6921,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.addOptInFlag(CmdArgs, options::OPT_mspeculative_load_hardening, options::OPT_mno_speculative_load_hardening); @@ -88,7 +76,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp RenderSCPOptions(TC, Args, CmdArgs); RenderTrivialAutoVarInitOptions(D, TC, Args, CmdArgs); -@@ -7535,6 +7594,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7535,6 +7589,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi options::OPT_fno_rewrite_imports, false); if (RewriteImports) CmdArgs.push_back("-frewrite-imports"); blob - d02d8d98de346b25ad07f6382e531825ca5979b2 (mode 644) blob + /dev/null --- devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp +++ /dev/null @@ -1,82 +0,0 @@ -Index: llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ---- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp.orig -+++ llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp -@@ -69,6 +69,7 @@ class MCInstrInfo; - - extern cl::opt<bool> EmitJalrReloc; - extern cl::opt<bool> NoZeroDivCheck; -+extern cl::opt<bool> FixLoongson2FBTB; - - namespace { - -@@ -236,6 +237,9 @@ class MipsAsmParser : public MCTargetAsmParser { - - bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); - -+ bool emitLoongson2FBTBFlush(MCInst &Inst, MipsTargetStreamer &TOut, -+ SMLoc IDLoc, const MCSubtargetInfo *STI); -+ - bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - MCStreamer &Out, const MCSubtargetInfo *STI); - -@@ -2060,6 +2064,20 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, S - Inst = BInst; - } - -+ if (FixLoongson2FBTB) { -+ switch (Inst.getOpcode()) { -+ case Mips::JALR: -+ case Mips::JR: -+ case Mips::JalOneReg: -+ case Mips::JalTwoReg: -+ if (emitLoongson2FBTBFlush(Inst, TOut, IDLoc, STI)) -+ return true; -+ LLVM_FALLTHROUGH; -+ default: -+ break; -+ } -+ } -+ - // This expansion is not in a function called by tryExpandInstruction() - // because the pseudo-instruction doesn't have a distinct opcode. - if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { -@@ -3356,6 +3374,39 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStrea - TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); - } - } -+ return false; -+} -+ -+bool MipsAsmParser::emitLoongson2FBTBFlush(MCInst &Inst, -+ MipsTargetStreamer &TOut, -+ SMLoc IDLoc, -+ const MCSubtargetInfo *STI) { -+ unsigned SReg = Inst.getOperand(0).getReg(); -+ if (SReg == Mips::ZERO || SReg == Mips::ZERO_64 || -+ SReg == Mips::K0 || SReg == Mips::K0_64 || -+ SReg == Mips::K1 || SReg == Mips::K1_64) -+ return false; -+ -+ unsigned ATReg = getATReg(IDLoc); -+ if (ATReg == 0) -+ return true; -+ -+ // Direct comparison of SReg and ATReg is not reliable because -+ // the register classes may differ. -+ unsigned ATRegIndex = AssemblerOptions.back()->getATRegIndex(); -+ if (ATRegIndex == 0) -+ return true; -+ if (SReg == getReg(Mips::GPR32RegClassID, ATRegIndex) || -+ SReg == getReg(Mips::GPR64RegClassID, ATRegIndex)) -+ return false; -+ -+ warnIfNoMacro(IDLoc); -+ -+ // li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ TOut.emitRRI(Mips::ORi, ATReg, Mips::ZERO, 3, IDLoc, STI); -+ // dmtc0 $at, COP_0_DIAG -+ TOut.emitRRI(Mips::DMTC0, Mips::COP022, ATReg, 0, IDLoc, STI); -+ - return false; - } - blob - a4373c933d582caffc21829f40bb2b5f94c6fbf4 blob + 969504464d309acb72778eca43a9b42748bb59dd --- devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt +++ devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt @@ -1,15 +1,7 @@ Index: llvm/lib/Target/Mips/CMakeLists.txt --- llvm/lib/Target/Mips/CMakeLists.txt.orig +++ llvm/lib/Target/Mips/CMakeLists.txt -@@ -45,6 +45,7 @@ add_llvm_target(MipsCodeGen - MipsISelLowering.cpp - MipsFrameLowering.cpp - MipsLegalizerInfo.cpp -+ MipsLoongson2FBTBFix.cpp - MipsBranchExpansion.cpp - MipsMCInstLower.cpp - MipsMachineFunction.cpp -@@ -55,6 +56,7 @@ add_llvm_target(MipsCodeGen +@@ -55,6 +55,7 @@ add_llvm_target(MipsCodeGen MipsPostLegalizerCombiner.cpp MipsRegisterBankInfo.cpp MipsRegisterInfo.cpp blob - 858a1f5479a5250f3bd7b51106591e230fa6874c (mode 644) blob + /dev/null --- devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp +++ /dev/null @@ -1,15 +0,0 @@ -Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp ---- llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp.orig -+++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp -@@ -25,6 +25,11 @@ cl::opt<bool> - cl::desc("MIPS: Don't trap on integer division by zero."), - cl::init(false)); - -+cl::opt<bool> -+FixLoongson2FBTB("fix-loongson2f-btb", cl::Hidden, -+ cl::desc("MIPS: Enable Loongson 2F BTB workaround"), -+ cl::init(false)); -+ - namespace { - static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; - blob - ea3b3c30fa82c65fa4e33ad4c95da9a0bf7864fd (mode 644) blob + /dev/null --- devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp +++ /dev/null @@ -1,95 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp ---- llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp.orig -+++ llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp -@@ -0,0 +1,91 @@ -+//===- MipsLoongson2FBTBFix.cpp -------------------------------------------===// -+// -+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -+// See https://llvm.org/LICENSE.txt for license information. -+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -+// -+//===----------------------------------------------------------------------===// -+ -+#include "Mips.h" -+#include "MipsTargetMachine.h" -+#include "llvm/CodeGen/MachineFunctionPass.h" -+#include "llvm/CodeGen/Passes.h" -+ -+using namespace llvm; -+ -+namespace { -+ -+class MipsLoongson2FBTBFix : public MachineFunctionPass { -+public: -+ static char ID; -+ -+ MipsLoongson2FBTBFix() : MachineFunctionPass(ID) { -+ initializeMipsLoongson2FBTBFixPass(*PassRegistry::getPassRegistry()); -+ } -+ -+ bool runOnMachineFunction(MachineFunction &MF) override; -+ -+ StringRef getPassName() const override { -+ return "Loongson 2F BTB erratum workaround pass"; -+ } -+ -+private: -+ bool runOnBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); -+}; -+ -+} // end of anonymous namespace -+ -+char MipsLoongson2FBTBFix::ID = 0; -+ -+INITIALIZE_PASS(MipsLoongson2FBTBFix, "loongson2f-btb-fix-pass", -+ "Mips Loongson 2F BTB erratum workaround", false, false) -+ -+FunctionPass *llvm::createMipsLoongson2FBTBFix() { -+ return new MipsLoongson2FBTBFix(); -+} -+ -+bool MipsLoongson2FBTBFix::runOnMachineFunction(MachineFunction &MF) { -+ bool Changed = false; -+ -+ for (auto &MBB : MF) { -+ Changed |= runOnBasicBlock(MF, MBB); -+ } -+ return Changed; -+} -+ -+bool MipsLoongson2FBTBFix::runOnBasicBlock( -+ MachineFunction &MF, MachineBasicBlock &MBB) { -+ MachineRegisterInfo &MRI = MF.getRegInfo(); -+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); -+ bool Changed = false; -+ -+ for (auto &MI : MBB) { -+ if (!MI.isCall() && !MI.isIndirectBranch() && !MI.isReturn()) -+ continue; -+ -+ // Skip calls that are not through a register. -+ if (MI.isCall()) { -+ if (MI.getNumOperands() == 0) -+ continue; -+ const MachineOperand &MO = MI.getOperand(0); -+ if (!MO.isReg()) -+ continue; -+ } -+ -+ Changed = true; -+ -+ DebugLoc MBBDL = MI.getDebugLoc(); -+ Register TempReg = MRI.createVirtualRegister(&Mips::GPR64RegClass); -+ -+ // li $TempReg, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::ORi), TempReg) -+ .addReg(Mips::ZERO) -+ .addImm(3); -+ // dmtc0 $TempReg, COP_0_DIAG -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::DMTC0)) -+ .addReg(Mips::COP022) -+ .addReg(TempReg) -+ .addImm(0); -+ } -+ return Changed; -+} blob - 6e1b66034f00b70fb0d5ae86574f5a18de70eac1 (mode 644) blob + /dev/null --- devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp +++ /dev/null @@ -1,21 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp ---- llvm/lib/Target/Mips/MipsTargetMachine.cpp.orig -+++ llvm/lib/Target/Mips/MipsTargetMachine.cpp -@@ -48,6 +48,7 @@ using namespace llvm; - - #define DEBUG_TYPE "mips" - -+extern cl::opt<bool> FixLoongson2FBTB; - static cl::opt<bool> - EnableMulMulFix("mfix4300", cl::init(false), - cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden); -@@ -253,6 +254,9 @@ bool MipsPassConfig::addInstSelector() { - - void MipsPassConfig::addPreRegAlloc() { - addPass(createMipsOptimizePICCallPass()); -+ -+ if (FixLoongson2FBTB) -+ addPass(createMipsLoongson2FBTBFix()); - } - - TargetTransformInfo blob - 9e8f5f8a382cd2765218b53fc902ff8072b2daf6 (mode 644) blob + /dev/null --- devel/clang-tools-extra/patches/patch-llvm_lib_Target_Mips_Mips_h +++ /dev/null @@ -1,19 +0,0 @@ -Index: llvm/lib/Target/Mips/Mips.h ---- llvm/lib/Target/Mips/Mips.h.orig -+++ llvm/lib/Target/Mips/Mips.h -@@ -41,6 +41,7 @@ class PassRegistry; - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - -+FunctionPass *createMipsLoongson2FBTBFix(); - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); -@@ -56,6 +57,7 @@ InstructionSelector * - createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, - const MipsRegisterBankInfo &); - -+void initializeMipsLoongson2FBTBFixPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsAsmPrinterPass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); blob - d1139eb87a12b259bae619e1c0ecf26296e1dc94 blob + 8e7117a521c7842f4510025232b17501d2227af8 --- devel/llvm/19/Makefile +++ devel/llvm/19/Makefile @@ -2,7 +2,7 @@ LLVM_MAJOR = 19 LLVM_VERSION = ${LLVM_MAJOR}.1.7 LLVM_PKGSPEC = <20 -REVISION-main = 14 +REVISION-main = 15 REVISION-libcxx = 1 REVISION-lldb = 2 REVISION-python = 2 blob - f7c3ed2ad49c0caa55b17dca7c010c8eefe35b6c blob + 783b006dbbdf5852fefb184bdedd2b45861b5757 --- devel/llvm/19/patches/patch-clang_include_clang_Driver_Options_td +++ devel/llvm/19/patches/patch-clang_include_clang_Driver_Options_td @@ -22,16 +22,7 @@ Index: clang/include/clang/Driver/Options.td def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-stop-after=">, Group<f_Group>, Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">, -@@ -5338,6 +5352,8 @@ def mno_check_zero_division : Flag<["-"], "mno-check-z - def mfix4300 : Flag<["-"], "mfix4300">, Group<m_mips_Features_Group>; - def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, - Group<m_mips_Features_Group>; -+def mfix_loongson2f_btb : Flag<["-"], "mfix-loongson2f-btb">, -+ Group<m_mips_Features_Group>; - } // let Flags = [TargetSpecific] - def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>, - IgnoredGCCCompat; -@@ -5554,10 +5570,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro +@@ -5554,10 +5568,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro def pedantic : Flag<["-", "--"], "pedantic">, Group<pedantic_Group>, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Warn on language extensions">, MarshallingInfoFlag<DiagnosticOpts<"Pedantic">>; @@ -47,7 +38,7 @@ Index: clang/include/clang/Driver/Options.td def pipe : Flag<["-", "--"], "pipe">, HelpText<"Use pipes between commands, when possible">; def prebind__all__twolevel__modules : Flag<["-"], "prebind_all_twolevel_modules">; -@@ -6368,6 +6388,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur +@@ -6368,6 +6386,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>; def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>; def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>; blob - 24a6bb1a65b40319b8d0a7c18da43ea15e574a79 blob + 6e8819bf5cbd382912215c4961a3f0d6b6678d68 --- devel/llvm/19/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp +++ devel/llvm/19/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp @@ -45,19 +45,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp StringRef ImplicitIt; for (const Arg *A : Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler, -@@ -2664,6 +2674,11 @@ static void CollectArgsForIntegratedAssembler(Compilat - CmdArgs.push_back("-soft-float"); - continue; - } -+ if (Value.starts_with("-mfix-loongson2f-btb")) { -+ CmdArgs.push_back("-mllvm"); -+ CmdArgs.push_back("-fix-loongson2f-btb"); -+ continue; -+ } - - MipsTargetFeature = llvm::StringSwitch<const char *>(Value) - .Case("-mips1", "+mips1") -@@ -2684,6 +2699,32 @@ static void CollectArgsForIntegratedAssembler(Compilat +@@ -2684,6 +2694,32 @@ static void CollectArgsForIntegratedAssembler(Compilat .Default(nullptr); if (MipsTargetFeature) continue; @@ -90,7 +78,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp } if (Value == "-force_cpusubtype_ALL") { -@@ -2791,6 +2832,21 @@ static void CollectArgsForIntegratedAssembler(Compilat +@@ -2791,6 +2827,21 @@ static void CollectArgsForIntegratedAssembler(Compilat CmdArgs.push_back(MipsTargetFeature); } @@ -112,7 +100,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp // forward -fembed-bitcode to assmebler if (C.getDriver().embedBitcodeEnabled() || C.getDriver().embedBitcodeMarkerOnly()) -@@ -5799,8 +5855,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -5799,8 +5850,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi OFastEnabled ? options::OPT_Ofast : options::OPT_fstrict_aliasing; // We turn strict aliasing off by default if we're Windows MSVC since MSVC // doesn't do any TBAA. @@ -126,7 +114,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp CmdArgs.push_back("-relaxed-aliasing"); if (Args.hasFlag(options::OPT_fpointer_tbaa, options::OPT_fno_pointer_tbaa, false)) -@@ -6844,7 +6904,8 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -6844,7 +6899,8 @@ void Clang::ConstructJob(Compilation &C, const JobActi options::OPT_fno_strict_overflow)) { if (A->getOption().matches(options::OPT_fno_strict_overflow)) CmdArgs.push_back("-fwrapv"); @@ -136,7 +124,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp Args.AddLastArg(CmdArgs, options::OPT_ffinite_loops, options::OPT_fno_finite_loops); -@@ -6860,7 +6921,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -6860,7 +6916,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.addOptInFlag(CmdArgs, options::OPT_mspeculative_load_hardening, options::OPT_mno_speculative_load_hardening); @@ -196,7 +184,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp RenderSCPOptions(TC, Args, CmdArgs); RenderTrivialAutoVarInitOptions(D, TC, Args, CmdArgs); -@@ -6938,6 +7050,11 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -6938,6 +7045,11 @@ void Clang::ConstructJob(Compilation &C, const JobActi if (Arg *A = Args.getLastArg(options::OPT_fcf_protection_EQ)) { CmdArgs.push_back( Args.MakeArgString(Twine("-fcf-protection=") + A->getValue())); @@ -208,7 +196,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp } if (Arg *A = Args.getLastArg(options::OPT_mfunction_return_EQ)) -@@ -7466,6 +7583,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7466,6 +7578,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi options::OPT_fno_rewrite_imports, false); if (RewriteImports) CmdArgs.push_back("-frewrite-imports"); blob - 52479360826914c2bc6d05cf2ff7ea5d472035f2 (mode 644) blob + /dev/null --- devel/llvm/19/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp +++ /dev/null @@ -1,82 +0,0 @@ -Index: llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ---- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp.orig -+++ llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp -@@ -69,6 +69,7 @@ class MCInstrInfo; - } // end namespace llvm - - extern cl::opt<bool> EmitJalrReloc; -+extern cl::opt<bool> FixLoongson2FBTB; - - namespace { - -@@ -235,6 +236,9 @@ class MipsAsmParser : public MCTargetAsmParser { - - bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); - -+ bool emitLoongson2FBTBFlush(MCInst &Inst, MipsTargetStreamer &TOut, -+ SMLoc IDLoc, const MCSubtargetInfo *STI); -+ - bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - MCStreamer &Out, const MCSubtargetInfo *STI); - -@@ -2104,6 +2108,20 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, S - Inst = BInst; - } - -+ if (FixLoongson2FBTB) { -+ switch (Inst.getOpcode()) { -+ case Mips::JALR: -+ case Mips::JR: -+ case Mips::JalOneReg: -+ case Mips::JalTwoReg: -+ if (emitLoongson2FBTBFlush(Inst, TOut, IDLoc, STI)) -+ return true; -+ LLVM_FALLTHROUGH; -+ default: -+ break; -+ } -+ } -+ - // This expansion is not in a function called by tryExpandInstruction() - // because the pseudo-instruction doesn't have a distinct opcode. - if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { -@@ -3404,6 +3422,39 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStrea - TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); - } - } -+ return false; -+} -+ -+bool MipsAsmParser::emitLoongson2FBTBFlush(MCInst &Inst, -+ MipsTargetStreamer &TOut, -+ SMLoc IDLoc, -+ const MCSubtargetInfo *STI) { -+ unsigned SReg = Inst.getOperand(0).getReg(); -+ if (SReg == Mips::ZERO || SReg == Mips::ZERO_64 || -+ SReg == Mips::K0 || SReg == Mips::K0_64 || -+ SReg == Mips::K1 || SReg == Mips::K1_64) -+ return false; -+ -+ unsigned ATReg = getATReg(IDLoc); -+ if (ATReg == 0) -+ return true; -+ -+ // Direct comparison of SReg and ATReg is not reliable because -+ // the register classes may differ. -+ unsigned ATRegIndex = AssemblerOptions.back()->getATRegIndex(); -+ if (ATRegIndex == 0) -+ return true; -+ if (SReg == getReg(Mips::GPR32RegClassID, ATRegIndex) || -+ SReg == getReg(Mips::GPR64RegClassID, ATRegIndex)) -+ return false; -+ -+ warnIfNoMacro(IDLoc); -+ -+ // li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ TOut.emitRRI(Mips::ORi, ATReg, Mips::ZERO, 3, IDLoc, STI); -+ // dmtc0 $at, COP_0_DIAG -+ TOut.emitRRI(Mips::DMTC0, Mips::COP022, ATReg, 0, IDLoc, STI); -+ - return false; - } - blob - 504b19f4493ffc32b1e3d3c0a0873e9b21c894e9 blob + c619c7c6300661122b04d5f33d7765205c5524a5 --- devel/llvm/19/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt +++ devel/llvm/19/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt @@ -1,15 +1,7 @@ Index: llvm/lib/Target/Mips/CMakeLists.txt --- llvm/lib/Target/Mips/CMakeLists.txt.orig +++ llvm/lib/Target/Mips/CMakeLists.txt -@@ -43,6 +43,7 @@ add_llvm_target(MipsCodeGen - MipsISelLowering.cpp - MipsFrameLowering.cpp - MipsLegalizerInfo.cpp -+ MipsLoongson2FBTBFix.cpp - MipsBranchExpansion.cpp - MipsMCInstLower.cpp - MipsMachineFunction.cpp -@@ -53,6 +54,7 @@ add_llvm_target(MipsCodeGen +@@ -53,6 +53,7 @@ add_llvm_target(MipsCodeGen MipsPostLegalizerCombiner.cpp MipsRegisterBankInfo.cpp MipsRegisterInfo.cpp blob - 21d801e0f0abefb1e13402a620a22917c0b5e436 (mode 644) blob + /dev/null --- devel/llvm/19/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp +++ /dev/null @@ -1,15 +0,0 @@ -Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp ---- llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp.orig -+++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp -@@ -22,6 +22,11 @@ EmitJalrReloc("mips-jalr-reloc", cl::Hidden, - cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"), - cl::init(true)); - -+cl::opt<bool> -+FixLoongson2FBTB("fix-loongson2f-btb", cl::Hidden, -+ cl::desc("MIPS: Enable Loongson 2F BTB workaround"), -+ cl::init(false)); -+ - namespace { - static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; - blob - ea3b3c30fa82c65fa4e33ad4c95da9a0bf7864fd (mode 644) blob + /dev/null --- devel/llvm/19/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp +++ /dev/null @@ -1,95 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp ---- llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp.orig -+++ llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp -@@ -0,0 +1,91 @@ -+//===- MipsLoongson2FBTBFix.cpp -------------------------------------------===// -+// -+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -+// See https://llvm.org/LICENSE.txt for license information. -+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -+// -+//===----------------------------------------------------------------------===// -+ -+#include "Mips.h" -+#include "MipsTargetMachine.h" -+#include "llvm/CodeGen/MachineFunctionPass.h" -+#include "llvm/CodeGen/Passes.h" -+ -+using namespace llvm; -+ -+namespace { -+ -+class MipsLoongson2FBTBFix : public MachineFunctionPass { -+public: -+ static char ID; -+ -+ MipsLoongson2FBTBFix() : MachineFunctionPass(ID) { -+ initializeMipsLoongson2FBTBFixPass(*PassRegistry::getPassRegistry()); -+ } -+ -+ bool runOnMachineFunction(MachineFunction &MF) override; -+ -+ StringRef getPassName() const override { -+ return "Loongson 2F BTB erratum workaround pass"; -+ } -+ -+private: -+ bool runOnBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); -+}; -+ -+} // end of anonymous namespace -+ -+char MipsLoongson2FBTBFix::ID = 0; -+ -+INITIALIZE_PASS(MipsLoongson2FBTBFix, "loongson2f-btb-fix-pass", -+ "Mips Loongson 2F BTB erratum workaround", false, false) -+ -+FunctionPass *llvm::createMipsLoongson2FBTBFix() { -+ return new MipsLoongson2FBTBFix(); -+} -+ -+bool MipsLoongson2FBTBFix::runOnMachineFunction(MachineFunction &MF) { -+ bool Changed = false; -+ -+ for (auto &MBB : MF) { -+ Changed |= runOnBasicBlock(MF, MBB); -+ } -+ return Changed; -+} -+ -+bool MipsLoongson2FBTBFix::runOnBasicBlock( -+ MachineFunction &MF, MachineBasicBlock &MBB) { -+ MachineRegisterInfo &MRI = MF.getRegInfo(); -+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); -+ bool Changed = false; -+ -+ for (auto &MI : MBB) { -+ if (!MI.isCall() && !MI.isIndirectBranch() && !MI.isReturn()) -+ continue; -+ -+ // Skip calls that are not through a register. -+ if (MI.isCall()) { -+ if (MI.getNumOperands() == 0) -+ continue; -+ const MachineOperand &MO = MI.getOperand(0); -+ if (!MO.isReg()) -+ continue; -+ } -+ -+ Changed = true; -+ -+ DebugLoc MBBDL = MI.getDebugLoc(); -+ Register TempReg = MRI.createVirtualRegister(&Mips::GPR64RegClass); -+ -+ // li $TempReg, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::ORi), TempReg) -+ .addReg(Mips::ZERO) -+ .addImm(3); -+ // dmtc0 $TempReg, COP_0_DIAG -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::DMTC0)) -+ .addReg(Mips::COP022) -+ .addReg(TempReg) -+ .addImm(0); -+ } -+ return Changed; -+} blob - 8d4fd17ba8cedf31178bc4eb1c8f12df801537e9 (mode 644) blob + /dev/null --- devel/llvm/19/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp +++ /dev/null @@ -1,21 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp ---- llvm/lib/Target/Mips/MipsTargetMachine.cpp.orig -+++ llvm/lib/Target/Mips/MipsTargetMachine.cpp -@@ -48,6 +48,7 @@ using namespace llvm; - - #define DEBUG_TYPE "mips" - -+extern cl::opt<bool> FixLoongson2FBTB; - static cl::opt<bool> - EnableMulMulFix("mfix4300", cl::init(false), - cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden); -@@ -280,6 +281,9 @@ bool MipsPassConfig::addInstSelector() { - - void MipsPassConfig::addPreRegAlloc() { - addPass(createMipsOptimizePICCallPass()); -+ -+ if (FixLoongson2FBTB) -+ addPass(createMipsLoongson2FBTBFix()); - } - - TargetTransformInfo blob - 511ccb245ec193cbbd4958c26b16a41e87895905 (mode 644) blob + /dev/null --- devel/llvm/19/patches/patch-llvm_lib_Target_Mips_Mips_h +++ /dev/null @@ -1,19 +0,0 @@ -Index: llvm/lib/Target/Mips/Mips.h ---- llvm/lib/Target/Mips/Mips.h.orig -+++ llvm/lib/Target/Mips/Mips.h -@@ -30,6 +30,7 @@ class PassRegistry; - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - -+FunctionPass *createMipsLoongson2FBTBFix(); - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); -@@ -45,6 +46,7 @@ InstructionSelector * - createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, - const MipsRegisterBankInfo &); - -+void initializeMipsLoongson2FBTBFixPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); - void initializeMipsDAGToDAGISelLegacyPass(PassRegistry &); blob - bec263cb08b95e4beac53549e67f4c71d13feade blob + 39336dfed350079b8284be1d4e56b85742def280 --- devel/llvm/20/Makefile +++ devel/llvm/20/Makefile @@ -5,7 +5,7 @@ LLVM_MAJOR = 20 LLVM_VERSION = ${LLVM_MAJOR}.1.8 LLVM_PKGSPEC = >=20,<21 -REVISION-main = 6 +REVISION-main = 7 REVISION-libcxx = 1 REVISION-lldb = 1 REVISION-python = 2 blob - 2ef20831bde2e1bd87284b776b6a0b8dbacc531e blob + 3c7e4b1e41404723229219cf5793a637241a020c --- devel/llvm/20/patches/patch-clang_include_clang_Driver_Options_td +++ devel/llvm/20/patches/patch-clang_include_clang_Driver_Options_td @@ -22,16 +22,7 @@ Index: clang/include/clang/Driver/Options.td def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-stop-after=">, Group<f_Group>, Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">, -@@ -5530,6 +5544,8 @@ def mno_check_zero_division : Flag<["-"], "mno-check-z - def mfix4300 : Flag<["-"], "mfix4300">, Group<m_mips_Features_Group>; - def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, - Group<m_mips_Features_Group>; -+def mfix_loongson2f_btb : Flag<["-"], "mfix-loongson2f-btb">, -+ Group<m_mips_Features_Group>; - } // let Flags = [TargetSpecific] - def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>, - IgnoredGCCCompat; -@@ -5760,10 +5776,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro +@@ -5760,10 +5774,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro def pedantic : Flag<["-", "--"], "pedantic">, Group<pedantic_Group>, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Warn on language extensions">, MarshallingInfoFlag<DiagnosticOpts<"Pedantic">>; @@ -47,7 +38,7 @@ Index: clang/include/clang/Driver/Options.td def pipe : Flag<["-", "--"], "pipe">, HelpText<"Use pipes between commands, when possible">; def prebind__all__twolevel__modules : Flag<["-"], "prebind_all_twolevel_modules">; -@@ -6618,6 +6638,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur +@@ -6618,6 +6636,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>; def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>; def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>; blob - 7c6365b76946b1deaba40a8642f6a5d642247087 blob + 3706bf27d4e66638afebb6dad7226da74becdec5 --- devel/llvm/20/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp +++ devel/llvm/20/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp @@ -98,19 +98,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp // forward -fembed-bitcode to assmebler if (C.getDriver().embedBitcodeEnabled() || C.getDriver().embedBitcodeMarkerOnly()) -@@ -3241,6 +3290,11 @@ static void RenderFloatingPointOptions(const ToolChain - << LastFpContractOverrideOption - << Args.MakeArgString("-ffp-contract=" + Val); - } -+ if (Val.starts_with("-mfix-loongson2f-btb")) { -+ CmdArgs.push_back("-mllvm"); -+ CmdArgs.push_back("-fix-loongson2f-btb"); -+ continue; -+ } - - FPContract = Val; - LastSeenFfpContractOption = Val; -@@ -5988,8 +6042,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -5988,8 +6037,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi OFastEnabled ? options::OPT_Ofast : options::OPT_fstrict_aliasing; // We turn strict aliasing off by default if we're Windows MSVC since MSVC // doesn't do any TBAA. @@ -124,7 +112,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp CmdArgs.push_back("-relaxed-aliasing"); if (Args.hasFlag(options::OPT_fno_pointer_tbaa, options::OPT_fpointer_tbaa, false)) -@@ -7051,7 +7109,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7051,7 +7104,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.addOptInFlag(CmdArgs, options::OPT_mspeculative_load_hardening, options::OPT_mno_speculative_load_hardening); @@ -184,7 +172,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp RenderSCPOptions(TC, Args, CmdArgs); RenderTrivialAutoVarInitOptions(D, TC, Args, CmdArgs); -@@ -7133,6 +7242,11 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7133,6 +7237,11 @@ void Clang::ConstructJob(Compilation &C, const JobActi if (Arg *SA = Args.getLastArg(options::OPT_mcf_branch_label_scheme_EQ)) CmdArgs.push_back(Args.MakeArgString(Twine("-mcf-branch-label-scheme=") + SA->getValue())); @@ -196,7 +184,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp } if (Arg *A = Args.getLastArg(options::OPT_mfunction_return_EQ)) -@@ -7666,6 +7780,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7666,6 +7775,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi options::OPT_fno_rewrite_imports, false); if (RewriteImports) CmdArgs.push_back("-frewrite-imports"); blob - f9ba388689e2e7a38db10d6cc8e15b487ade83de (mode 644) blob + /dev/null --- devel/llvm/20/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp +++ /dev/null @@ -1,82 +0,0 @@ -Index: llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ---- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp.orig -+++ llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp -@@ -68,6 +68,7 @@ class MCInstrInfo; - } // end namespace llvm - - extern cl::opt<bool> EmitJalrReloc; -+extern cl::opt<bool> FixLoongson2FBTB; - - namespace { - -@@ -234,6 +235,9 @@ class MipsAsmParser : public MCTargetAsmParser { - - bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); - -+ bool emitLoongson2FBTBFlush(MCInst &Inst, MipsTargetStreamer &TOut, -+ SMLoc IDLoc, const MCSubtargetInfo *STI); -+ - bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - MCStreamer &Out, const MCSubtargetInfo *STI); - -@@ -2103,6 +2107,20 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, S - Inst = BInst; - } - -+ if (FixLoongson2FBTB) { -+ switch (Inst.getOpcode()) { -+ case Mips::JALR: -+ case Mips::JR: -+ case Mips::JalOneReg: -+ case Mips::JalTwoReg: -+ if (emitLoongson2FBTBFlush(Inst, TOut, IDLoc, STI)) -+ return true; -+ LLVM_FALLTHROUGH; -+ default: -+ break; -+ } -+ } -+ - // This expansion is not in a function called by tryExpandInstruction() - // because the pseudo-instruction doesn't have a distinct opcode. - if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { -@@ -3407,6 +3425,39 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStrea - TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); - } - } -+ return false; -+} -+ -+bool MipsAsmParser::emitLoongson2FBTBFlush(MCInst &Inst, -+ MipsTargetStreamer &TOut, -+ SMLoc IDLoc, -+ const MCSubtargetInfo *STI) { -+ unsigned SReg = Inst.getOperand(0).getReg(); -+ if (SReg == Mips::ZERO || SReg == Mips::ZERO_64 || -+ SReg == Mips::K0 || SReg == Mips::K0_64 || -+ SReg == Mips::K1 || SReg == Mips::K1_64) -+ return false; -+ -+ unsigned ATReg = getATReg(IDLoc); -+ if (ATReg == 0) -+ return true; -+ -+ // Direct comparison of SReg and ATReg is not reliable because -+ // the register classes may differ. -+ unsigned ATRegIndex = AssemblerOptions.back()->getATRegIndex(); -+ if (ATRegIndex == 0) -+ return true; -+ if (SReg == getReg(Mips::GPR32RegClassID, ATRegIndex) || -+ SReg == getReg(Mips::GPR64RegClassID, ATRegIndex)) -+ return false; -+ -+ warnIfNoMacro(IDLoc); -+ -+ // li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ TOut.emitRRI(Mips::ORi, ATReg, Mips::ZERO, 3, IDLoc, STI); -+ // dmtc0 $at, COP_0_DIAG -+ TOut.emitRRI(Mips::DMTC0, Mips::COP022, ATReg, 0, IDLoc, STI); -+ - return false; - } - blob - 504b19f4493ffc32b1e3d3c0a0873e9b21c894e9 blob + c619c7c6300661122b04d5f33d7765205c5524a5 --- devel/llvm/20/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt +++ devel/llvm/20/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt @@ -1,15 +1,7 @@ Index: llvm/lib/Target/Mips/CMakeLists.txt --- llvm/lib/Target/Mips/CMakeLists.txt.orig +++ llvm/lib/Target/Mips/CMakeLists.txt -@@ -43,6 +43,7 @@ add_llvm_target(MipsCodeGen - MipsISelLowering.cpp - MipsFrameLowering.cpp - MipsLegalizerInfo.cpp -+ MipsLoongson2FBTBFix.cpp - MipsBranchExpansion.cpp - MipsMCInstLower.cpp - MipsMachineFunction.cpp -@@ -53,6 +54,7 @@ add_llvm_target(MipsCodeGen +@@ -53,6 +53,7 @@ add_llvm_target(MipsCodeGen MipsPostLegalizerCombiner.cpp MipsRegisterBankInfo.cpp MipsRegisterInfo.cpp blob - cdc229843c4fee3b4769fded49c227fade5c04d2 (mode 644) blob + /dev/null --- devel/llvm/20/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp +++ /dev/null @@ -1,15 +0,0 @@ -Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp ---- llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp.orig -+++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp -@@ -21,6 +21,11 @@ EmitJalrReloc("mips-jalr-reloc", cl::Hidden, - cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"), - cl::init(true)); - -+cl::opt<bool> -+FixLoongson2FBTB("fix-loongson2f-btb", cl::Hidden, -+ cl::desc("MIPS: Enable Loongson 2F BTB workaround"), -+ cl::init(false)); -+ - namespace { - static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; - blob - ea3b3c30fa82c65fa4e33ad4c95da9a0bf7864fd (mode 644) blob + /dev/null --- devel/llvm/20/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp +++ /dev/null @@ -1,95 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp ---- llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp.orig -+++ llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp -@@ -0,0 +1,91 @@ -+//===- MipsLoongson2FBTBFix.cpp -------------------------------------------===// -+// -+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -+// See https://llvm.org/LICENSE.txt for license information. -+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -+// -+//===----------------------------------------------------------------------===// -+ -+#include "Mips.h" -+#include "MipsTargetMachine.h" -+#include "llvm/CodeGen/MachineFunctionPass.h" -+#include "llvm/CodeGen/Passes.h" -+ -+using namespace llvm; -+ -+namespace { -+ -+class MipsLoongson2FBTBFix : public MachineFunctionPass { -+public: -+ static char ID; -+ -+ MipsLoongson2FBTBFix() : MachineFunctionPass(ID) { -+ initializeMipsLoongson2FBTBFixPass(*PassRegistry::getPassRegistry()); -+ } -+ -+ bool runOnMachineFunction(MachineFunction &MF) override; -+ -+ StringRef getPassName() const override { -+ return "Loongson 2F BTB erratum workaround pass"; -+ } -+ -+private: -+ bool runOnBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); -+}; -+ -+} // end of anonymous namespace -+ -+char MipsLoongson2FBTBFix::ID = 0; -+ -+INITIALIZE_PASS(MipsLoongson2FBTBFix, "loongson2f-btb-fix-pass", -+ "Mips Loongson 2F BTB erratum workaround", false, false) -+ -+FunctionPass *llvm::createMipsLoongson2FBTBFix() { -+ return new MipsLoongson2FBTBFix(); -+} -+ -+bool MipsLoongson2FBTBFix::runOnMachineFunction(MachineFunction &MF) { -+ bool Changed = false; -+ -+ for (auto &MBB : MF) { -+ Changed |= runOnBasicBlock(MF, MBB); -+ } -+ return Changed; -+} -+ -+bool MipsLoongson2FBTBFix::runOnBasicBlock( -+ MachineFunction &MF, MachineBasicBlock &MBB) { -+ MachineRegisterInfo &MRI = MF.getRegInfo(); -+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); -+ bool Changed = false; -+ -+ for (auto &MI : MBB) { -+ if (!MI.isCall() && !MI.isIndirectBranch() && !MI.isReturn()) -+ continue; -+ -+ // Skip calls that are not through a register. -+ if (MI.isCall()) { -+ if (MI.getNumOperands() == 0) -+ continue; -+ const MachineOperand &MO = MI.getOperand(0); -+ if (!MO.isReg()) -+ continue; -+ } -+ -+ Changed = true; -+ -+ DebugLoc MBBDL = MI.getDebugLoc(); -+ Register TempReg = MRI.createVirtualRegister(&Mips::GPR64RegClass); -+ -+ // li $TempReg, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::ORi), TempReg) -+ .addReg(Mips::ZERO) -+ .addImm(3); -+ // dmtc0 $TempReg, COP_0_DIAG -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::DMTC0)) -+ .addReg(Mips::COP022) -+ .addReg(TempReg) -+ .addImm(0); -+ } -+ return Changed; -+} blob - 3047a22b271fed0e58fb34b5b574871b3d299aaf (mode 644) blob + /dev/null --- devel/llvm/20/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp +++ /dev/null @@ -1,21 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp ---- llvm/lib/Target/Mips/MipsTargetMachine.cpp.orig -+++ llvm/lib/Target/Mips/MipsTargetMachine.cpp -@@ -47,6 +47,7 @@ using namespace llvm; - - #define DEBUG_TYPE "mips" - -+extern cl::opt<bool> FixLoongson2FBTB; - static cl::opt<bool> - EnableMulMulFix("mfix4300", cl::init(false), - cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden); -@@ -286,6 +287,9 @@ bool MipsPassConfig::addInstSelector() { - - void MipsPassConfig::addPreRegAlloc() { - addPass(createMipsOptimizePICCallPass()); -+ -+ if (FixLoongson2FBTB) -+ addPass(createMipsLoongson2FBTBFix()); - } - - TargetTransformInfo blob - 707bc2494517c567b81a8a2e4e86e9026cc159ba (mode 644) blob + /dev/null --- devel/llvm/20/patches/patch-llvm_lib_Target_Mips_Mips_h +++ /dev/null @@ -1,19 +0,0 @@ -Index: llvm/lib/Target/Mips/Mips.h ---- llvm/lib/Target/Mips/Mips.h.orig -+++ llvm/lib/Target/Mips/Mips.h -@@ -41,6 +41,7 @@ class PassRegistry; - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - -+FunctionPass *createMipsLoongson2FBTBFix(); - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); -@@ -56,6 +57,7 @@ InstructionSelector * - createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, - const MipsRegisterBankInfo &); - -+void initializeMipsLoongson2FBTBFixPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); - void initializeMipsDAGToDAGISelLegacyPass(PassRegistry &); blob - cf0b520a9baa8ba87e4d9ddd510bd90ea8e50722 blob + 374832b2e2d61f1a89b83d6fd1f8f6a4462b7c06 --- devel/llvm/21/Makefile +++ devel/llvm/21/Makefile @@ -2,7 +2,7 @@ LLVM_MAJOR = 21 LLVM_VERSION = ${LLVM_MAJOR}.1.8 LLVM_PKGSPEC = >=21,<22 -REVISION-main = 4 +REVISION-main = 5 REVISION-lldb = 2 REVISION-libcxx = 2 REVISION-python = 3 blob - b4a8bdafe2296855807dc2532b8647c82a11c779 blob + 77da5fd39f1c62351b5c6f50540a571194c2be13 --- devel/llvm/21/patches/patch-clang_include_clang_Driver_Options_td +++ devel/llvm/21/patches/patch-clang_include_clang_Driver_Options_td @@ -22,16 +22,7 @@ Index: clang/include/clang/Driver/Options.td def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-stop-after=">, Group<f_Group>, Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">, -@@ -5676,6 +5690,8 @@ def mno_check_zero_division : Flag<["-"], "mno-check-z - def mfix4300 : Flag<["-"], "mfix4300">, Group<m_mips_Features_Group>; - def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, - Group<m_mips_Features_Group>; -+def mfix_loongson2f_btb : Flag<["-"], "mfix-loongson2f-btb">, -+ Group<m_mips_Features_Group>; - } // let Flags = [TargetSpecific] - def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>, - IgnoredGCCCompat; -@@ -5919,10 +5935,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro +@@ -5919,10 +5933,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro def pedantic : Flag<["-", "--"], "pedantic">, Group<pedantic_Group>, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Warn on language extensions">, MarshallingInfoFlag<DiagnosticOpts<"Pedantic">>; @@ -47,7 +38,7 @@ Index: clang/include/clang/Driver/Options.td def pipe : Flag<["-", "--"], "pipe">, HelpText<"Use pipes between commands, when possible">; def prebind__all__twolevel__modules : Flag<["-"], "prebind_all_twolevel_modules">; -@@ -6780,6 +6800,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur +@@ -6780,6 +6798,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>; def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>; def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>; blob - 4d3e21c94948dfbb967574763540b7c73092d15d blob + f512a78b414d239f9971b38b76806a2a5416b20f --- devel/llvm/21/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp +++ devel/llvm/21/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp @@ -1,19 +1,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp --- clang/lib/Driver/ToolChains/Clang.cpp.orig +++ clang/lib/Driver/ToolChains/Clang.cpp -@@ -3111,6 +3111,11 @@ static void RenderFloatingPointOptions(const ToolChain - << LastFpContractOverrideOption - << Args.MakeArgString("-ffp-contract=" + Val); - } -+ if (Val.starts_with("-mfix-loongson2f-btb")) { -+ CmdArgs.push_back("-mllvm"); -+ CmdArgs.push_back("-fix-loongson2f-btb"); -+ continue; -+ } - - FPContract = Val; - LastSeenFfpContractOption = Val; -@@ -5822,9 +5827,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -5822,9 +5822,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi OFastEnabled ? options::OPT_Ofast : options::OPT_fstrict_aliasing; // We turn strict aliasing off by default if we're Windows MSVC since MSVC // doesn't do any TBAA. @@ -28,7 +16,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp CmdArgs.push_back("-relaxed-aliasing"); if (Args.hasFlag(options::OPT_fno_pointer_tbaa, options::OPT_fpointer_tbaa, false)) -@@ -6896,7 +6904,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -6896,7 +6899,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.addOptInFlag(CmdArgs, options::OPT_mspeculative_load_hardening, options::OPT_mno_speculative_load_hardening); @@ -88,7 +76,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp RenderSCPOptions(TC, Args, CmdArgs); RenderTrivialAutoVarInitOptions(D, TC, Args, CmdArgs); -@@ -7508,6 +7567,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7508,6 +7562,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi options::OPT_fno_rewrite_imports, false); if (RewriteImports) CmdArgs.push_back("-frewrite-imports"); blob - 5bb726afcdf02b5ad642f6be6c49300ca8a33251 (mode 644) blob + /dev/null --- devel/llvm/21/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp +++ /dev/null @@ -1,82 +0,0 @@ -Index: llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ---- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp.orig -+++ llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp -@@ -68,6 +68,7 @@ class MCInstrInfo; - } // end namespace llvm - - extern cl::opt<bool> EmitJalrReloc; -+extern cl::opt<bool> FixLoongson2FBTB; - - namespace { - -@@ -235,6 +236,9 @@ class MipsAsmParser : public MCTargetAsmParser { - - bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); - -+ bool emitLoongson2FBTBFlush(MCInst &Inst, MipsTargetStreamer &TOut, -+ SMLoc IDLoc, const MCSubtargetInfo *STI); -+ - bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - MCStreamer &Out, const MCSubtargetInfo *STI); - -@@ -2058,6 +2062,20 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, S - Inst = BInst; - } - -+ if (FixLoongson2FBTB) { -+ switch (Inst.getOpcode()) { -+ case Mips::JALR: -+ case Mips::JR: -+ case Mips::JalOneReg: -+ case Mips::JalTwoReg: -+ if (emitLoongson2FBTBFlush(Inst, TOut, IDLoc, STI)) -+ return true; -+ LLVM_FALLTHROUGH; -+ default: -+ break; -+ } -+ } -+ - // This expansion is not in a function called by tryExpandInstruction() - // because the pseudo-instruction doesn't have a distinct opcode. - if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { -@@ -3353,6 +3371,39 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStrea - TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); - } - } -+ return false; -+} -+ -+bool MipsAsmParser::emitLoongson2FBTBFlush(MCInst &Inst, -+ MipsTargetStreamer &TOut, -+ SMLoc IDLoc, -+ const MCSubtargetInfo *STI) { -+ unsigned SReg = Inst.getOperand(0).getReg(); -+ if (SReg == Mips::ZERO || SReg == Mips::ZERO_64 || -+ SReg == Mips::K0 || SReg == Mips::K0_64 || -+ SReg == Mips::K1 || SReg == Mips::K1_64) -+ return false; -+ -+ unsigned ATReg = getATReg(IDLoc); -+ if (ATReg == 0) -+ return true; -+ -+ // Direct comparison of SReg and ATReg is not reliable because -+ // the register classes may differ. -+ unsigned ATRegIndex = AssemblerOptions.back()->getATRegIndex(); -+ if (ATRegIndex == 0) -+ return true; -+ if (SReg == getReg(Mips::GPR32RegClassID, ATRegIndex) || -+ SReg == getReg(Mips::GPR64RegClassID, ATRegIndex)) -+ return false; -+ -+ warnIfNoMacro(IDLoc); -+ -+ // li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ TOut.emitRRI(Mips::ORi, ATReg, Mips::ZERO, 3, IDLoc, STI); -+ // dmtc0 $at, COP_0_DIAG -+ TOut.emitRRI(Mips::DMTC0, Mips::COP022, ATReg, 0, IDLoc, STI); -+ - return false; - } - blob - 504b19f4493ffc32b1e3d3c0a0873e9b21c894e9 blob + c619c7c6300661122b04d5f33d7765205c5524a5 --- devel/llvm/21/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt +++ devel/llvm/21/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt @@ -1,15 +1,7 @@ Index: llvm/lib/Target/Mips/CMakeLists.txt --- llvm/lib/Target/Mips/CMakeLists.txt.orig +++ llvm/lib/Target/Mips/CMakeLists.txt -@@ -43,6 +43,7 @@ add_llvm_target(MipsCodeGen - MipsISelLowering.cpp - MipsFrameLowering.cpp - MipsLegalizerInfo.cpp -+ MipsLoongson2FBTBFix.cpp - MipsBranchExpansion.cpp - MipsMCInstLower.cpp - MipsMachineFunction.cpp -@@ -53,6 +54,7 @@ add_llvm_target(MipsCodeGen +@@ -53,6 +53,7 @@ add_llvm_target(MipsCodeGen MipsPostLegalizerCombiner.cpp MipsRegisterBankInfo.cpp MipsRegisterInfo.cpp blob - cdc229843c4fee3b4769fded49c227fade5c04d2 (mode 644) blob + /dev/null --- devel/llvm/21/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp +++ /dev/null @@ -1,15 +0,0 @@ -Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp ---- llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp.orig -+++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp -@@ -21,6 +21,11 @@ EmitJalrReloc("mips-jalr-reloc", cl::Hidden, - cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"), - cl::init(true)); - -+cl::opt<bool> -+FixLoongson2FBTB("fix-loongson2f-btb", cl::Hidden, -+ cl::desc("MIPS: Enable Loongson 2F BTB workaround"), -+ cl::init(false)); -+ - namespace { - static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; - blob - ea3b3c30fa82c65fa4e33ad4c95da9a0bf7864fd (mode 644) blob + /dev/null --- devel/llvm/21/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp +++ /dev/null @@ -1,95 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp ---- llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp.orig -+++ llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp -@@ -0,0 +1,91 @@ -+//===- MipsLoongson2FBTBFix.cpp -------------------------------------------===// -+// -+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -+// See https://llvm.org/LICENSE.txt for license information. -+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -+// -+//===----------------------------------------------------------------------===// -+ -+#include "Mips.h" -+#include "MipsTargetMachine.h" -+#include "llvm/CodeGen/MachineFunctionPass.h" -+#include "llvm/CodeGen/Passes.h" -+ -+using namespace llvm; -+ -+namespace { -+ -+class MipsLoongson2FBTBFix : public MachineFunctionPass { -+public: -+ static char ID; -+ -+ MipsLoongson2FBTBFix() : MachineFunctionPass(ID) { -+ initializeMipsLoongson2FBTBFixPass(*PassRegistry::getPassRegistry()); -+ } -+ -+ bool runOnMachineFunction(MachineFunction &MF) override; -+ -+ StringRef getPassName() const override { -+ return "Loongson 2F BTB erratum workaround pass"; -+ } -+ -+private: -+ bool runOnBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); -+}; -+ -+} // end of anonymous namespace -+ -+char MipsLoongson2FBTBFix::ID = 0; -+ -+INITIALIZE_PASS(MipsLoongson2FBTBFix, "loongson2f-btb-fix-pass", -+ "Mips Loongson 2F BTB erratum workaround", false, false) -+ -+FunctionPass *llvm::createMipsLoongson2FBTBFix() { -+ return new MipsLoongson2FBTBFix(); -+} -+ -+bool MipsLoongson2FBTBFix::runOnMachineFunction(MachineFunction &MF) { -+ bool Changed = false; -+ -+ for (auto &MBB : MF) { -+ Changed |= runOnBasicBlock(MF, MBB); -+ } -+ return Changed; -+} -+ -+bool MipsLoongson2FBTBFix::runOnBasicBlock( -+ MachineFunction &MF, MachineBasicBlock &MBB) { -+ MachineRegisterInfo &MRI = MF.getRegInfo(); -+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); -+ bool Changed = false; -+ -+ for (auto &MI : MBB) { -+ if (!MI.isCall() && !MI.isIndirectBranch() && !MI.isReturn()) -+ continue; -+ -+ // Skip calls that are not through a register. -+ if (MI.isCall()) { -+ if (MI.getNumOperands() == 0) -+ continue; -+ const MachineOperand &MO = MI.getOperand(0); -+ if (!MO.isReg()) -+ continue; -+ } -+ -+ Changed = true; -+ -+ DebugLoc MBBDL = MI.getDebugLoc(); -+ Register TempReg = MRI.createVirtualRegister(&Mips::GPR64RegClass); -+ -+ // li $TempReg, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::ORi), TempReg) -+ .addReg(Mips::ZERO) -+ .addImm(3); -+ // dmtc0 $TempReg, COP_0_DIAG -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::DMTC0)) -+ .addReg(Mips::COP022) -+ .addReg(TempReg) -+ .addImm(0); -+ } -+ return Changed; -+} blob - e9d83fb21bc1ed01dd62e9f42107c70c489e6ec0 (mode 644) blob + /dev/null --- devel/llvm/21/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp +++ /dev/null @@ -1,21 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp ---- llvm/lib/Target/Mips/MipsTargetMachine.cpp.orig -+++ llvm/lib/Target/Mips/MipsTargetMachine.cpp -@@ -48,6 +48,7 @@ using namespace llvm; - - #define DEBUG_TYPE "mips" - -+extern cl::opt<bool> FixLoongson2FBTB; - static cl::opt<bool> - EnableMulMulFix("mfix4300", cl::init(false), - cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden); -@@ -289,6 +290,9 @@ bool MipsPassConfig::addInstSelector() { - - void MipsPassConfig::addPreRegAlloc() { - addPass(createMipsOptimizePICCallPass()); -+ -+ if (FixLoongson2FBTB) -+ addPass(createMipsLoongson2FBTBFix()); - } - - TargetTransformInfo blob - 9e8f5f8a382cd2765218b53fc902ff8072b2daf6 (mode 644) blob + /dev/null --- devel/llvm/21/patches/patch-llvm_lib_Target_Mips_Mips_h +++ /dev/null @@ -1,19 +0,0 @@ -Index: llvm/lib/Target/Mips/Mips.h ---- llvm/lib/Target/Mips/Mips.h.orig -+++ llvm/lib/Target/Mips/Mips.h -@@ -41,6 +41,7 @@ class PassRegistry; - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - -+FunctionPass *createMipsLoongson2FBTBFix(); - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); -@@ -56,6 +57,7 @@ InstructionSelector * - createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, - const MipsRegisterBankInfo &); - -+void initializeMipsLoongson2FBTBFixPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsAsmPrinterPass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); blob - 778a7d06b15923494fa01234a4d6c2dc8486fb47 blob + d41a9d4ac66420ebf60dca318d2543885a4662ec --- devel/llvm/22/Makefile +++ devel/llvm/22/Makefile @@ -2,7 +2,7 @@ LLVM_MAJOR = 22 LLVM_VERSION = ${LLVM_MAJOR}.1.8 LLVM_PKGSPEC = >=22,<23 -REVISION-main = 1 +REVISION-main = 2 REVISION-libcxx = 0 REVISION-lldb = 0 REVISION-python = 0 blob - cacef63a8679267b7edf2b8f7a9652d4fb9cd4e3 blob + 073d246881aacd1101ff9a67b46f6c5846591103 --- devel/llvm/22/patches/patch-clang_include_clang_Options_Options_td +++ devel/llvm/22/patches/patch-clang_include_clang_Options_Options_td @@ -22,16 +22,7 @@ Index: clang/include/clang/Options/Options.td def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-stop-after=">, Group<f_Group>, Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">, -@@ -5912,6 +5926,8 @@ def mno_check_zero_division : Flag<["-"], "mno-check-z - def mfix4300 : Flag<["-"], "mfix4300">, Group<m_mips_Features_Group>; - def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, - Group<m_mips_Features_Group>; -+def mfix_loongson2f_btb : Flag<["-"], "mfix-loongson2f-btb">, -+ Group<m_mips_Features_Group>; - } // let Flags = [TargetSpecific] - def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>, - IgnoredGCCCompat; -@@ -6154,10 +6170,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro +@@ -6154,10 +6168,14 @@ def pedantic_errors : Flag<["-", "--"], "pedantic-erro def pedantic : Flag<["-", "--"], "pedantic">, Group<pedantic_Group>, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Warn on language extensions">, MarshallingInfoFlag<DiagnosticOpts<"Pedantic">>; @@ -47,7 +38,7 @@ Index: clang/include/clang/Options/Options.td def pipe : Flag<["-", "--"], "pipe">, HelpText<"Use pipes between commands, when possible">; def prebind__all__twolevel__modules : Flag<["-"], "prebind_all_twolevel_modules">; -@@ -7007,6 +7027,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur +@@ -7007,6 +7025,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Featur def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>; def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>; def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>; blob - 7a9114adfcdeacf412035d04c2a1ca587a9a6e69 blob + 75ca5ab5bb5b5db8becaf85972e54a4857c549f7 --- devel/llvm/22/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp +++ devel/llvm/22/patches/patch-clang_lib_Driver_ToolChains_Clang_cpp @@ -1,19 +1,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp --- clang/lib/Driver/ToolChains/Clang.cpp.orig +++ clang/lib/Driver/ToolChains/Clang.cpp -@@ -3044,6 +3044,11 @@ static void RenderFloatingPointOptions(const ToolChain - << LastFpContractOverrideOption - << Args.MakeArgString("-ffp-contract=" + Val); - } -+ if (Val.starts_with("-mfix-loongson2f-btb")) { -+ CmdArgs.push_back("-mllvm"); -+ CmdArgs.push_back("-fix-loongson2f-btb"); -+ continue; -+ } - - FPContract = Val; - LastSeenFfpContractOption = Val; -@@ -5807,9 +5812,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -5807,9 +5807,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi OFastEnabled ? options::OPT_Ofast : options::OPT_fstrict_aliasing; // We turn strict aliasing off by default if we're Windows MSVC since MSVC // doesn't do any TBAA. @@ -28,7 +16,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp CmdArgs.push_back("-relaxed-aliasing"); if (Args.hasFlag(options::OPT_fno_pointer_tbaa, options::OPT_fpointer_tbaa, false)) -@@ -6918,7 +6926,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -6918,7 +6921,58 @@ void Clang::ConstructJob(Compilation &C, const JobActi Args.addOptInFlag(CmdArgs, options::OPT_mspeculative_load_hardening, options::OPT_mno_speculative_load_hardening); @@ -88,7 +76,7 @@ Index: clang/lib/Driver/ToolChains/Clang.cpp RenderSCPOptions(TC, Args, CmdArgs); RenderTrivialAutoVarInitOptions(D, TC, Args, CmdArgs); -@@ -7535,6 +7594,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi +@@ -7535,6 +7589,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi options::OPT_fno_rewrite_imports, false); if (RewriteImports) CmdArgs.push_back("-frewrite-imports"); blob - d02d8d98de346b25ad07f6382e531825ca5979b2 (mode 644) blob + /dev/null --- devel/llvm/22/patches/patch-llvm_lib_Target_Mips_AsmParser_MipsAsmParser_cpp +++ /dev/null @@ -1,82 +0,0 @@ -Index: llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ---- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp.orig -+++ llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp -@@ -69,6 +69,7 @@ class MCInstrInfo; - - extern cl::opt<bool> EmitJalrReloc; - extern cl::opt<bool> NoZeroDivCheck; -+extern cl::opt<bool> FixLoongson2FBTB; - - namespace { - -@@ -236,6 +237,9 @@ class MipsAsmParser : public MCTargetAsmParser { - - bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); - -+ bool emitLoongson2FBTBFlush(MCInst &Inst, MipsTargetStreamer &TOut, -+ SMLoc IDLoc, const MCSubtargetInfo *STI); -+ - bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, - MCStreamer &Out, const MCSubtargetInfo *STI); - -@@ -2060,6 +2064,20 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, S - Inst = BInst; - } - -+ if (FixLoongson2FBTB) { -+ switch (Inst.getOpcode()) { -+ case Mips::JALR: -+ case Mips::JR: -+ case Mips::JalOneReg: -+ case Mips::JalTwoReg: -+ if (emitLoongson2FBTBFlush(Inst, TOut, IDLoc, STI)) -+ return true; -+ LLVM_FALLTHROUGH; -+ default: -+ break; -+ } -+ } -+ - // This expansion is not in a function called by tryExpandInstruction() - // because the pseudo-instruction doesn't have a distinct opcode. - if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { -@@ -3356,6 +3374,39 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStrea - TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); - } - } -+ return false; -+} -+ -+bool MipsAsmParser::emitLoongson2FBTBFlush(MCInst &Inst, -+ MipsTargetStreamer &TOut, -+ SMLoc IDLoc, -+ const MCSubtargetInfo *STI) { -+ unsigned SReg = Inst.getOperand(0).getReg(); -+ if (SReg == Mips::ZERO || SReg == Mips::ZERO_64 || -+ SReg == Mips::K0 || SReg == Mips::K0_64 || -+ SReg == Mips::K1 || SReg == Mips::K1_64) -+ return false; -+ -+ unsigned ATReg = getATReg(IDLoc); -+ if (ATReg == 0) -+ return true; -+ -+ // Direct comparison of SReg and ATReg is not reliable because -+ // the register classes may differ. -+ unsigned ATRegIndex = AssemblerOptions.back()->getATRegIndex(); -+ if (ATRegIndex == 0) -+ return true; -+ if (SReg == getReg(Mips::GPR32RegClassID, ATRegIndex) || -+ SReg == getReg(Mips::GPR64RegClassID, ATRegIndex)) -+ return false; -+ -+ warnIfNoMacro(IDLoc); -+ -+ // li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ TOut.emitRRI(Mips::ORi, ATReg, Mips::ZERO, 3, IDLoc, STI); -+ // dmtc0 $at, COP_0_DIAG -+ TOut.emitRRI(Mips::DMTC0, Mips::COP022, ATReg, 0, IDLoc, STI); -+ - return false; - } - blob - a4373c933d582caffc21829f40bb2b5f94c6fbf4 blob + 969504464d309acb72778eca43a9b42748bb59dd --- devel/llvm/22/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt +++ devel/llvm/22/patches/patch-llvm_lib_Target_Mips_CMakeLists_txt @@ -1,15 +1,7 @@ Index: llvm/lib/Target/Mips/CMakeLists.txt --- llvm/lib/Target/Mips/CMakeLists.txt.orig +++ llvm/lib/Target/Mips/CMakeLists.txt -@@ -45,6 +45,7 @@ add_llvm_target(MipsCodeGen - MipsISelLowering.cpp - MipsFrameLowering.cpp - MipsLegalizerInfo.cpp -+ MipsLoongson2FBTBFix.cpp - MipsBranchExpansion.cpp - MipsMCInstLower.cpp - MipsMachineFunction.cpp -@@ -55,6 +56,7 @@ add_llvm_target(MipsCodeGen +@@ -55,6 +55,7 @@ add_llvm_target(MipsCodeGen MipsPostLegalizerCombiner.cpp MipsRegisterBankInfo.cpp MipsRegisterInfo.cpp blob - 858a1f5479a5250f3bd7b51106591e230fa6874c (mode 644) blob + /dev/null --- devel/llvm/22/patches/patch-llvm_lib_Target_Mips_MCTargetDesc_MipsABIInfo_cpp +++ /dev/null @@ -1,15 +0,0 @@ -Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp ---- llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp.orig -+++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp -@@ -25,6 +25,11 @@ cl::opt<bool> - cl::desc("MIPS: Don't trap on integer division by zero."), - cl::init(false)); - -+cl::opt<bool> -+FixLoongson2FBTB("fix-loongson2f-btb", cl::Hidden, -+ cl::desc("MIPS: Enable Loongson 2F BTB workaround"), -+ cl::init(false)); -+ - namespace { - static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; - blob - ea3b3c30fa82c65fa4e33ad4c95da9a0bf7864fd (mode 644) blob + /dev/null --- devel/llvm/22/patches/patch-llvm_lib_Target_Mips_MipsLoongson2FBTBFix_cpp +++ /dev/null @@ -1,95 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp ---- llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp.orig -+++ llvm/lib/Target/Mips/MipsLoongson2FBTBFix.cpp -@@ -0,0 +1,91 @@ -+//===- MipsLoongson2FBTBFix.cpp -------------------------------------------===// -+// -+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -+// See https://llvm.org/LICENSE.txt for license information. -+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -+// -+//===----------------------------------------------------------------------===// -+ -+#include "Mips.h" -+#include "MipsTargetMachine.h" -+#include "llvm/CodeGen/MachineFunctionPass.h" -+#include "llvm/CodeGen/Passes.h" -+ -+using namespace llvm; -+ -+namespace { -+ -+class MipsLoongson2FBTBFix : public MachineFunctionPass { -+public: -+ static char ID; -+ -+ MipsLoongson2FBTBFix() : MachineFunctionPass(ID) { -+ initializeMipsLoongson2FBTBFixPass(*PassRegistry::getPassRegistry()); -+ } -+ -+ bool runOnMachineFunction(MachineFunction &MF) override; -+ -+ StringRef getPassName() const override { -+ return "Loongson 2F BTB erratum workaround pass"; -+ } -+ -+private: -+ bool runOnBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); -+}; -+ -+} // end of anonymous namespace -+ -+char MipsLoongson2FBTBFix::ID = 0; -+ -+INITIALIZE_PASS(MipsLoongson2FBTBFix, "loongson2f-btb-fix-pass", -+ "Mips Loongson 2F BTB erratum workaround", false, false) -+ -+FunctionPass *llvm::createMipsLoongson2FBTBFix() { -+ return new MipsLoongson2FBTBFix(); -+} -+ -+bool MipsLoongson2FBTBFix::runOnMachineFunction(MachineFunction &MF) { -+ bool Changed = false; -+ -+ for (auto &MBB : MF) { -+ Changed |= runOnBasicBlock(MF, MBB); -+ } -+ return Changed; -+} -+ -+bool MipsLoongson2FBTBFix::runOnBasicBlock( -+ MachineFunction &MF, MachineBasicBlock &MBB) { -+ MachineRegisterInfo &MRI = MF.getRegInfo(); -+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); -+ bool Changed = false; -+ -+ for (auto &MI : MBB) { -+ if (!MI.isCall() && !MI.isIndirectBranch() && !MI.isReturn()) -+ continue; -+ -+ // Skip calls that are not through a register. -+ if (MI.isCall()) { -+ if (MI.getNumOperands() == 0) -+ continue; -+ const MachineOperand &MO = MI.getOperand(0); -+ if (!MO.isReg()) -+ continue; -+ } -+ -+ Changed = true; -+ -+ DebugLoc MBBDL = MI.getDebugLoc(); -+ Register TempReg = MRI.createVirtualRegister(&Mips::GPR64RegClass); -+ -+ // li $TempReg, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::ORi), TempReg) -+ .addReg(Mips::ZERO) -+ .addImm(3); -+ // dmtc0 $TempReg, COP_0_DIAG -+ BuildMI(MBB, MI, MBBDL, TII->get(Mips::DMTC0)) -+ .addReg(Mips::COP022) -+ .addReg(TempReg) -+ .addImm(0); -+ } -+ return Changed; -+} blob - 6e1b66034f00b70fb0d5ae86574f5a18de70eac1 (mode 644) blob + /dev/null --- devel/llvm/22/patches/patch-llvm_lib_Target_Mips_MipsTargetMachine_cpp +++ /dev/null @@ -1,21 +0,0 @@ -Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp ---- llvm/lib/Target/Mips/MipsTargetMachine.cpp.orig -+++ llvm/lib/Target/Mips/MipsTargetMachine.cpp -@@ -48,6 +48,7 @@ using namespace llvm; - - #define DEBUG_TYPE "mips" - -+extern cl::opt<bool> FixLoongson2FBTB; - static cl::opt<bool> - EnableMulMulFix("mfix4300", cl::init(false), - cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden); -@@ -253,6 +254,9 @@ bool MipsPassConfig::addInstSelector() { - - void MipsPassConfig::addPreRegAlloc() { - addPass(createMipsOptimizePICCallPass()); -+ -+ if (FixLoongson2FBTB) -+ addPass(createMipsLoongson2FBTBFix()); - } - - TargetTransformInfo blob - 9e8f5f8a382cd2765218b53fc902ff8072b2daf6 (mode 644) blob + /dev/null --- devel/llvm/22/patches/patch-llvm_lib_Target_Mips_Mips_h +++ /dev/null @@ -1,19 +0,0 @@ -Index: llvm/lib/Target/Mips/Mips.h ---- llvm/lib/Target/Mips/Mips.h.orig -+++ llvm/lib/Target/Mips/Mips.h -@@ -41,6 +41,7 @@ class PassRegistry; - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - -+FunctionPass *createMipsLoongson2FBTBFix(); - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); -@@ -56,6 +57,7 @@ InstructionSelector * - createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, - const MipsRegisterBankInfo &); - -+void initializeMipsLoongson2FBTBFixPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsAsmPrinterPass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); -- Christian "naddy" Weisgerber naddy@mips.inka.de